qemu-patch-raspberry4/target/riscv
Dayeol Lee 49db9fa1fd
target/riscv: Fix PMP range boundary address bug
A wrong address is passed to `pmp_is_in_range` while checking if a
memory access is within a PMP range.
Since the ending address of the pmp range (i.e., pmp_state.addr[i].ea)
is set to the last address in the range (i.e., pmp base + pmp size - 1),
memory accesses containg the last address in the range will always fail.

For example, assume that a PMP range is 4KB from 0x87654000 such that
the last address within the range is 0x87654fff.
1-byte access to 0x87654fff should be considered to be fully inside the
PMP range.
However the access now fails and complains partial inclusion because
pmp_is_in_range(env, i, addr + size) returns 0 whereas
pmp_is_in_range(env, i, addr) returns 1.

Signed-off-by: Dayeol Lee <dayeol@berkeley.edu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-23 23:44:41 -07:00
..
insn_trans target/riscv: Split gen_arith_imm into functional and temp 2019-05-24 12:09:23 -07:00
cpu-param.h tcg: Split out target/arch/cpu-param.h 2019-06-10 07:03:34 -07:00
cpu.c target/riscv: Allow setting ISA extensions via CPU props 2019-06-23 23:44:41 -07:00
cpu.h target/riscv: Allow setting ISA extensions via CPU props 2019-06-23 23:44:41 -07:00
cpu_bits.h Supply missing header guards 2019-06-12 13:20:21 +02:00
cpu_helper.c target/riscv: Use env_cpu, env_archcpu 2019-06-10 07:03:42 -07:00
cpu_user.h Supply missing header guards 2019-06-12 13:20:21 +02:00
csr.c target/riscv: Use env_cpu, env_archcpu 2019-06-10 07:03:42 -07:00
fpu_helper.c RISC-V: Use riscv prefix consistently on cpu helpers 2019-02-11 15:56:21 -08:00
gdbstub.c Include qemu-common.h exactly where needed 2019-06-12 13:20:20 +02:00
helper.h RISC-V CPU Helpers 2018-03-07 08:30:28 +13:00
insn16-32.decode target/riscv: Split RVC32 and RVC64 insns into separate files 2019-05-24 12:09:22 -07:00
insn16-64.decode target/riscv: Add checks for several RVC reserved operands 2019-05-24 12:09:25 -07:00
insn16.decode target/riscv: Add checks for several RVC reserved operands 2019-05-24 12:09:25 -07:00
insn32-64.decode target/riscv: Convert RV64D insns to decodetree 2019-03-13 10:34:06 +01:00
insn32.decode target/riscv: Name the argument sets for all of insn32 formats 2019-05-24 12:09:22 -07:00
instmap.h Supply missing header guards 2019-06-12 13:20:21 +02:00
Makefile.objs target/riscv: Split RVC32 and RVC64 insns into separate files 2019-05-24 12:09:22 -07:00
op_helper.c target/riscv: Use env_cpu, env_archcpu 2019-06-10 07:03:42 -07:00
pmp.c target/riscv: Fix PMP range boundary address bug 2019-06-23 23:44:41 -07:00
pmp.h Clean up ill-advised or unusual header guards 2019-05-13 08:58:55 +02:00
trace-events RISC-V: Convert trap debugging to trace events 2019-03-19 05:14:40 -07:00
translate.c target/riscv: Split gen_arith_imm into functional and temp 2019-05-24 12:09:23 -07:00