4b19de14b1
The IRQ Route Control registers definitions belong to the PIIX chipset. We were only defining the 'A' register. Define the other B, C and D registers, and use them. Acked-by: Paul Durrant <paul@xen.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
39 lines
1 KiB
C
39 lines
1 KiB
C
/*
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* QEMU PIIX South Bridge Emulation
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*
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* Copyright (c) 2006 Fabrice Bellard
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* Copyright (c) 2018 Hervé Poussineau
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#ifndef HW_SOUTHBRIDGE_PIIX_H
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#define HW_SOUTHBRIDGE_PIIX_H
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#define TYPE_PIIX4_PM "PIIX4_PM"
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I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
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qemu_irq sci_irq, qemu_irq smi_irq,
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int smm_enabled, DeviceState **piix4_pm);
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/* PIRQRC[A:D]: PIRQx Route Control Registers */
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#define PIIX_PIRQCA 0x60
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#define PIIX_PIRQCB 0x61
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#define PIIX_PIRQCC 0x62
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#define PIIX_PIRQCD 0x63
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/*
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* Reset Control Register: PCI-accessible ISA-Compatible Register at address
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* 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
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*/
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#define PIIX_RCR_IOPORT 0xcf9
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extern PCIDevice *piix4_dev;
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DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
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I2CBus **smbus, size_t ide_buses);
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#endif
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