4c3119a6e3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180308223946.26784-11-f4bug@amsat.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
94 lines
3.1 KiB
C
94 lines
3.1 KiB
C
/*
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* Generic ISA Super I/O
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*
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* Copyright (c) 2010-2012 Herve Poussineau
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* Copyright (c) 2011-2012 Andreas Färber
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* Copyright (c) 2018 Philippe Mathieu-Daudé
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*
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* This code is licensed under the GNU GPLv2 and later.
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* See the COPYING file in the top-level directory.
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "qemu/error-report.h"
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#include "sysemu/sysemu.h"
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#include "chardev/char.h"
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#include "hw/isa/superio.h"
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#include "trace.h"
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static void isa_superio_realize(DeviceState *dev, Error **errp)
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{
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ISASuperIODevice *sio = ISA_SUPERIO(dev);
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ISASuperIOClass *k = ISA_SUPERIO_GET_CLASS(sio);
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ISABus *bus = isa_bus_from_device(ISA_DEVICE(dev));
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ISADevice *isa;
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DeviceState *d;
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Chardev *chr;
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char *name;
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int i;
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/* Parallel port */
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for (i = 0; i < k->parallel.count; i++) {
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if (i >= ARRAY_SIZE(sio->parallel)) {
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warn_report("superio: ignoring %td parallel controllers",
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k->parallel.count - ARRAY_SIZE(sio->parallel));
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break;
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}
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if (!k->parallel.is_enabled || k->parallel.is_enabled(sio, i)) {
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/* FIXME use a qdev chardev prop instead of parallel_hds[] */
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chr = parallel_hds[i];
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if (chr == NULL || chr->be) {
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name = g_strdup_printf("discarding-parallel%d", i);
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chr = qemu_chr_new(name, "null");
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} else {
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name = g_strdup_printf("parallel%d", i);
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}
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isa = isa_create(bus, "isa-parallel");
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d = DEVICE(isa);
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qdev_prop_set_uint32(d, "index", i);
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if (k->parallel.get_iobase) {
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qdev_prop_set_uint32(d, "iobase",
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k->parallel.get_iobase(sio, i));
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}
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if (k->parallel.get_irq) {
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qdev_prop_set_uint32(d, "irq", k->parallel.get_irq(sio, i));
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}
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qdev_prop_set_chr(d, "chardev", chr);
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qdev_init_nofail(d);
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sio->parallel[i] = isa;
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trace_superio_create_parallel(i,
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k->parallel.get_iobase ?
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k->parallel.get_iobase(sio, i) : -1,
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k->parallel.get_irq ?
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k->parallel.get_irq(sio, i) : -1);
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object_property_add_child(OBJECT(dev), name,
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OBJECT(sio->parallel[i]), NULL);
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g_free(name);
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}
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}
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}
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static void isa_superio_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->realize = isa_superio_realize;
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/* Reason: Uses parallel_hds[0] in realize(), so it can't be used twice */
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dc->user_creatable = false;
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}
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static const TypeInfo isa_superio_type_info = {
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.name = TYPE_ISA_SUPERIO,
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.parent = TYPE_ISA_DEVICE,
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.abstract = true,
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.class_size = sizeof(ISASuperIOClass),
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.class_init = isa_superio_class_init,
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};
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static void isa_superio_register_types(void)
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{
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type_register_static(&isa_superio_type_info);
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}
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type_init(isa_superio_register_types)
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