In commit102ca9667d
we set "start-powered-off" on all vCPUs included in the CPS (Coherent Processing System) but forgot to start the vCPUS on when they are powered on in the CPC (Cluster Power Controller). This fixes the following tests: $ avocado run tests/acceptance/machine_mips_malta.py (1/3) test_mips_malta_i6400_framebuffer_logo_1core: PASS (3.67 s) (2/3) test_mips_malta_i6400_framebuffer_logo_7cores: INTERRUPTED: Test interrupted by SIGTERM (30.22 s) (3/3) test_mips_malta_i6400_framebuffer_logo_8cores: INTERRUPTED: Test interrupted by SIGTERM (30.25 s) RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 2 | CANCEL 0 Fixes:102ca9667d
("mips/cps: Use start-powered-off CPUState property") Reported-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20201007113942.2523866-1-f4bug@amsat.org> Message-Id: <20201007160038.26953-3-alex.bennee@linaro.org>
196 lines
5.2 KiB
C
196 lines
5.2 KiB
C
/*
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* Cluster Power Controller emulation
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*
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* Copyright (c) 2016 Imagination Technologies
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "hw/misc/mips_cpc.h"
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#include "hw/qdev-properties.h"
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static inline uint64_t cpc_vp_run_mask(MIPSCPCState *cpc)
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{
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return (1ULL << cpc->num_vp) - 1;
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}
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static void mips_cpu_reset_async_work(CPUState *cs, run_on_cpu_data data)
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{
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MIPSCPCState *cpc = (MIPSCPCState *) data.host_ptr;
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cpu_reset(cs);
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cs->halted = 0;
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cpc->vp_running |= 1ULL << cs->cpu_index;
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}
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static void cpc_run_vp(MIPSCPCState *cpc, uint64_t vp_run)
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{
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CPUState *cs = first_cpu;
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CPU_FOREACH(cs) {
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uint64_t i = 1ULL << cs->cpu_index;
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if (i & vp_run & ~cpc->vp_running) {
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/*
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* To avoid racing with a CPU we are just kicking off.
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* We do the final bit of preparation for the work in
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* the target CPUs context.
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*/
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async_safe_run_on_cpu(cs, mips_cpu_reset_async_work,
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RUN_ON_CPU_HOST_PTR(cpc));
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}
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}
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}
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static void cpc_stop_vp(MIPSCPCState *cpc, uint64_t vp_stop)
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{
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CPUState *cs = first_cpu;
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CPU_FOREACH(cs) {
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uint64_t i = 1ULL << cs->cpu_index;
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if (i & vp_stop & cpc->vp_running) {
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cpu_interrupt(cs, CPU_INTERRUPT_HALT);
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cpc->vp_running &= ~i;
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}
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}
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}
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static void cpc_write(void *opaque, hwaddr offset, uint64_t data,
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unsigned size)
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{
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MIPSCPCState *s = opaque;
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switch (offset) {
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case CPC_CL_BASE_OFS + CPC_VP_RUN_OFS:
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case CPC_CO_BASE_OFS + CPC_VP_RUN_OFS:
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cpc_run_vp(s, data & cpc_vp_run_mask(s));
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break;
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case CPC_CL_BASE_OFS + CPC_VP_STOP_OFS:
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case CPC_CO_BASE_OFS + CPC_VP_STOP_OFS:
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cpc_stop_vp(s, data & cpc_vp_run_mask(s));
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break;
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default:
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qemu_log_mask(LOG_UNIMP,
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"%s: Bad offset 0x%x\n", __func__, (int)offset);
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break;
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}
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return;
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}
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static uint64_t cpc_read(void *opaque, hwaddr offset, unsigned size)
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{
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MIPSCPCState *s = opaque;
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switch (offset) {
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case CPC_CL_BASE_OFS + CPC_VP_RUNNING_OFS:
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case CPC_CO_BASE_OFS + CPC_VP_RUNNING_OFS:
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return s->vp_running;
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default:
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qemu_log_mask(LOG_UNIMP,
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"%s: Bad offset 0x%x\n", __func__, (int)offset);
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return 0;
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}
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}
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static const MemoryRegionOps cpc_ops = {
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.read = cpc_read,
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.write = cpc_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.impl = {
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.max_access_size = 8,
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},
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};
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static void mips_cpc_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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MIPSCPCState *s = MIPS_CPC(obj);
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memory_region_init_io(&s->mr, OBJECT(s), &cpc_ops, s, "mips-cpc",
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CPC_ADDRSPACE_SZ);
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sysbus_init_mmio(sbd, &s->mr);
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}
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static void mips_cpc_realize(DeviceState *dev, Error **errp)
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{
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MIPSCPCState *s = MIPS_CPC(dev);
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if (s->vp_start_running > cpc_vp_run_mask(s)) {
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error_setg(errp,
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"incorrect vp_start_running 0x%" PRIx64 " for num_vp = %d",
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s->vp_running, s->num_vp);
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return;
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}
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}
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static void mips_cpc_reset(DeviceState *dev)
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{
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MIPSCPCState *s = MIPS_CPC(dev);
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/* Reflect the fact that all VPs are halted on reset */
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s->vp_running = 0;
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/* Put selected VPs into run state */
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cpc_run_vp(s, s->vp_start_running);
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}
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static const VMStateDescription vmstate_mips_cpc = {
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.name = "mips-cpc",
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.version_id = 0,
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.minimum_version_id = 0,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(vp_running, MIPSCPCState),
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VMSTATE_END_OF_LIST()
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},
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};
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static Property mips_cpc_properties[] = {
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DEFINE_PROP_UINT32("num-vp", MIPSCPCState, num_vp, 0x1),
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DEFINE_PROP_UINT64("vp-start-running", MIPSCPCState, vp_start_running, 0x1),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void mips_cpc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = mips_cpc_realize;
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dc->reset = mips_cpc_reset;
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dc->vmsd = &vmstate_mips_cpc;
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device_class_set_props(dc, mips_cpc_properties);
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}
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static const TypeInfo mips_cpc_info = {
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.name = TYPE_MIPS_CPC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(MIPSCPCState),
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.instance_init = mips_cpc_init,
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.class_init = mips_cpc_class_init,
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};
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static void mips_cpc_register_types(void)
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{
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type_register_static(&mips_cpc_info);
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}
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type_init(mips_cpc_register_types)
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