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qemu-patch-raspberry4/target-arm
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Benjamin Herrenschmidt 97ed5ccdee tlb: Add "ifetch" argument to cpu_mmu_index() 
This is set to true when the index is for an instruction fetch
translation.

The core get_page_addr_code() sets it, as do the SOFTMMU_CODE_ACCESS
acessors.

All targets ignore it for now, and all other callers pass "false".

This will allow targets who wish to split the mmu index between
instruction and data accesses to do so. A subsequent patch will
do just that for PowerPC.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Message-Id: <1439796853-4410-2-git-send-email-benh@kernel.crashing.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-11 08:15:28 -07:00
..
arm-semi.c target-arm/arm-semi.c: SYS_EXIT on A64 takes a parameter block 2015-09-07 10:39:28 +01:00
arm_ldst.h softmmu: introduce cpu_ldst.h 2014-06-05 16:10:33 +02:00
cpu-qom.h target-arm: Refactor CPU affinity handling 2015-09-07 10:39:31 +01:00
cpu.c target-arm: Refactor CPU affinity handling 2015-09-07 10:39:31 +01:00
cpu.h tlb: Add "ifetch" argument to cpu_mmu_index() 2015-09-11 08:15:28 -07:00
cpu64.c target-arm: Fix REVIDR reset value 2015-06-15 18:06:08 +01:00
crypto_helper.c crypto: move built-in AES implementation into crypto/ 2015-07-07 12:04:13 +02:00
gdbstub.c cpu: Introduce CPUClass::gdb_{read,write}_register() 2013-07-27 00:04:17 +02:00
gdbstub64.c target-arm/gdbstub64.c: remove useless 'break' statement. 2014-04-17 21:34:06 +01:00
helper-a64.c target-arm: Log the target EL when taking exceptions 2015-09-08 17:38:44 +01:00
helper-a64.h target-arm: A64: Implement CRC instructions 2014-06-09 16:06:12 +01:00
helper.c tlb: Add "ifetch" argument to cpu_mmu_index() 2015-09-11 08:15:28 -07:00
helper.h target-arm: Split DISAS_YIELD from DISAS_WFE 2015-07-06 10:05:44 +01:00
internals.h target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction 2015-09-07 10:39:28 +01:00
iwmmxt_helper.c target-arm: Delete unused iwmmxt_msadb helper 2014-06-09 16:06:12 +01:00
kvm-consts.h target-arm/kvm64: Add cortex-a53 cpu support 2015-06-15 18:06:08 +01:00
kvm-stub.c target-arm: kvm: Differentiate registers based on write-back levels 2015-07-21 11:18:45 +01:00
kvm.c target-arm: kvm: Differentiate registers based on write-back levels 2015-07-21 11:18:45 +01:00
kvm32.c target-arm: Refactor CPU affinity handling 2015-09-07 10:39:31 +01:00
kvm64.c target-arm: Refactor CPU affinity handling 2015-09-07 10:39:31 +01:00
kvm_arm.h Introduce gic_class_name() instead of repeating condition 2015-08-13 11:26:21 +01:00
machine.c target-arm: kvm: Differentiate registers based on write-back levels 2015-07-21 11:18:45 +01:00
Makefile.objs target-arm: add emulation of PSCI calls for system emulation 2014-10-24 12:19:13 +01:00
neon_helper.c target-arm: add support for v8 VMULL.P64 instruction 2014-06-09 16:06:11 +01:00
op_addsub.h Correct spelling of licensed 2011-07-23 11:26:12 -05:00
op_helper.c target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2, 3 2015-08-25 15:45:08 +01:00
psci.c target-arm: Use the kernel's idea of MPIDR if we're using KVM 2015-06-15 18:06:09 +01:00
translate-a64.c target-arm: Fix default_exception_el() function for the case when EL3 is not supported 2015-09-08 17:38:44 +01:00
translate.c maint: remove / fix many doubled words 2015-09-11 10:21:38 +03:00
translate.h target-arm: Fix default_exception_el() function for the case when EL3 is not supported 2015-09-08 17:38:44 +01:00