This patch makes NPCM7XX Timer to use a the timer clock generated by the CLK module instead of the magic number TIMER_REF_HZ. Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com> Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Signed-off-by: Hao Wu <wuhaotsh@google.com> Message-id: 20210108190945.949196-3-wuhaotsh@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
181 lines
5.1 KiB
C
181 lines
5.1 KiB
C
/*
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* Nuvoton NPCM7xx Clock Control Registers.
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*
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* Copyright 2020 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#ifndef NPCM7XX_CLK_H
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#define NPCM7XX_CLK_H
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#include "exec/memory.h"
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#include "hw/clock.h"
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#include "hw/sysbus.h"
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/*
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* Number of registers in our device state structure. Don't change this without
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* incrementing the version_id in the vmstate.
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*/
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#define NPCM7XX_CLK_NR_REGS (0x70 / sizeof(uint32_t))
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#define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in"
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/* Maximum amount of clock inputs in a SEL module. */
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#define NPCM7XX_CLK_SEL_MAX_INPUT 5
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/* PLLs in CLK module. */
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typedef enum NPCM7xxClockPLL {
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NPCM7XX_CLOCK_PLL0,
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NPCM7XX_CLOCK_PLL1,
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NPCM7XX_CLOCK_PLL2,
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NPCM7XX_CLOCK_PLLG,
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NPCM7XX_CLOCK_NR_PLLS,
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} NPCM7xxClockPLL;
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/* SEL/MUX in CLK module. */
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typedef enum NPCM7xxClockSEL {
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NPCM7XX_CLOCK_PIXCKSEL,
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NPCM7XX_CLOCK_MCCKSEL,
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NPCM7XX_CLOCK_CPUCKSEL,
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NPCM7XX_CLOCK_CLKOUTSEL,
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NPCM7XX_CLOCK_UARTCKSEL,
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NPCM7XX_CLOCK_TIMCKSEL,
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NPCM7XX_CLOCK_SDCKSEL,
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NPCM7XX_CLOCK_GFXMSEL,
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NPCM7XX_CLOCK_SUCKSEL,
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NPCM7XX_CLOCK_NR_SELS,
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} NPCM7xxClockSEL;
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/* Dividers in CLK module. */
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typedef enum NPCM7xxClockDivider {
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NPCM7XX_CLOCK_PLL1D2, /* PLL1/2 */
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NPCM7XX_CLOCK_PLL2D2, /* PLL2/2 */
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NPCM7XX_CLOCK_MC_DIVIDER,
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NPCM7XX_CLOCK_AXI_DIVIDER,
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NPCM7XX_CLOCK_AHB_DIVIDER,
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NPCM7XX_CLOCK_AHB3_DIVIDER,
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NPCM7XX_CLOCK_SPI0_DIVIDER,
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NPCM7XX_CLOCK_SPIX_DIVIDER,
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NPCM7XX_CLOCK_APB1_DIVIDER,
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NPCM7XX_CLOCK_APB2_DIVIDER,
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NPCM7XX_CLOCK_APB3_DIVIDER,
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NPCM7XX_CLOCK_APB4_DIVIDER,
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NPCM7XX_CLOCK_APB5_DIVIDER,
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NPCM7XX_CLOCK_CLKOUT_DIVIDER,
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NPCM7XX_CLOCK_UART_DIVIDER,
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NPCM7XX_CLOCK_TIMER_DIVIDER,
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NPCM7XX_CLOCK_ADC_DIVIDER,
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NPCM7XX_CLOCK_MMC_DIVIDER,
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NPCM7XX_CLOCK_SDHC_DIVIDER,
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NPCM7XX_CLOCK_GFXM_DIVIDER, /* divide by 3 */
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NPCM7XX_CLOCK_UTMI_DIVIDER,
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NPCM7XX_CLOCK_NR_DIVIDERS,
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} NPCM7xxClockConverter;
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typedef struct NPCM7xxCLKState NPCM7xxCLKState;
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/**
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* struct NPCM7xxClockPLLState - A PLL module in CLK module.
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* @name: The name of the module.
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* @clk: The CLK module that owns this module.
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* @clock_in: The input clock of this module.
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* @clock_out: The output clock of this module.
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* @reg: The control registers for this PLL module.
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*/
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typedef struct NPCM7xxClockPLLState {
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DeviceState parent;
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const char *name;
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NPCM7xxCLKState *clk;
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Clock *clock_in;
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Clock *clock_out;
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int reg;
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} NPCM7xxClockPLLState;
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/**
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* struct NPCM7xxClockSELState - A SEL module in CLK module.
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* @name: The name of the module.
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* @clk: The CLK module that owns this module.
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* @input_size: The size of inputs of this module.
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* @clock_in: The input clocks of this module.
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* @clock_out: The output clocks of this module.
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* @offset: The offset of this module in the control register.
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* @len: The length of this module in the control register.
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*/
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typedef struct NPCM7xxClockSELState {
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DeviceState parent;
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const char *name;
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NPCM7xxCLKState *clk;
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uint8_t input_size;
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Clock *clock_in[NPCM7XX_CLK_SEL_MAX_INPUT];
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Clock *clock_out;
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int offset;
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int len;
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} NPCM7xxClockSELState;
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/**
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* struct NPCM7xxClockDividerState - A Divider module in CLK module.
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* @name: The name of the module.
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* @clk: The CLK module that owns this module.
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* @clock_in: The input clock of this module.
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* @clock_out: The output clock of this module.
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* @divide: The function the divider uses to divide the input.
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* @reg: The index of the control register that contains the divisor.
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* @offset: The offset of the divisor in the control register.
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* @len: The length of the divisor in the control register.
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* @divisor: The divisor for a constant divisor
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*/
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typedef struct NPCM7xxClockDividerState {
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DeviceState parent;
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const char *name;
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NPCM7xxCLKState *clk;
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Clock *clock_in;
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Clock *clock_out;
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uint32_t (*divide)(struct NPCM7xxClockDividerState *s);
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union {
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struct {
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int reg;
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int offset;
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int len;
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};
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int divisor;
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};
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} NPCM7xxClockDividerState;
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struct NPCM7xxCLKState {
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SysBusDevice parent;
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MemoryRegion iomem;
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/* Clock converters */
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NPCM7xxClockPLLState plls[NPCM7XX_CLOCK_NR_PLLS];
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NPCM7xxClockSELState sels[NPCM7XX_CLOCK_NR_SELS];
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NPCM7xxClockDividerState dividers[NPCM7XX_CLOCK_NR_DIVIDERS];
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uint32_t regs[NPCM7XX_CLK_NR_REGS];
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/* Time reference for SECCNT and CNTR25M, initialized by power on reset */
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int64_t ref_ns;
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/* The incoming reference clock. */
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Clock *clkref;
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};
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#define TYPE_NPCM7XX_CLK "npcm7xx-clk"
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#define NPCM7XX_CLK(obj) OBJECT_CHECK(NPCM7xxCLKState, (obj), TYPE_NPCM7XX_CLK)
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#endif /* NPCM7XX_CLK_H */
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