Move all the frontend struct and methods to a seperate unit. This avoids accidentally mixing backend and frontend calls, and helps with readabilty. Make qemu_chr_replay() a macro shared by both char and char-fe. Export qemu_chr_write(), and use a macro for qemu_chr_write_all() (nb: yes, CharBackend is for char frontend :) Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
567 lines
16 KiB
C
567 lines
16 KiB
C
/*
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* Device model for Cadence UART
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*
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* Reference: Xilinx Zynq 7000 reference manual
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* - http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
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* - Chapter 19 UART Controller
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* - Appendix B for Register details
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*
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* Copyright (c) 2010 Xilinx Inc.
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* Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
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* Copyright (c) 2012 PetaLogix Pty Ltd.
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* Written by Haibing Ma
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* M.Habib
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "chardev/char-fe.h"
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#include "chardev/char-serial.h"
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#include "qemu/timer.h"
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#include "qemu/log.h"
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#include "hw/char/cadence_uart.h"
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#ifdef CADENCE_UART_ERR_DEBUG
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#define DB_PRINT(...) do { \
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fprintf(stderr, ": %s: ", __func__); \
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fprintf(stderr, ## __VA_ARGS__); \
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} while (0);
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#else
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#define DB_PRINT(...)
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#endif
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#define UART_SR_INTR_RTRIG 0x00000001
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#define UART_SR_INTR_REMPTY 0x00000002
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#define UART_SR_INTR_RFUL 0x00000004
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#define UART_SR_INTR_TEMPTY 0x00000008
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#define UART_SR_INTR_TFUL 0x00000010
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/* somewhat awkwardly, TTRIG is misaligned between SR and ISR */
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#define UART_SR_TTRIG 0x00002000
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#define UART_INTR_TTRIG 0x00000400
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/* bits fields in CSR that correlate to CISR. If any of these bits are set in
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* SR, then the same bit in CISR is set high too */
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#define UART_SR_TO_CISR_MASK 0x0000001F
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#define UART_INTR_ROVR 0x00000020
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#define UART_INTR_FRAME 0x00000040
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#define UART_INTR_PARE 0x00000080
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#define UART_INTR_TIMEOUT 0x00000100
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#define UART_INTR_DMSI 0x00000200
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#define UART_INTR_TOVR 0x00001000
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#define UART_SR_RACTIVE 0x00000400
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#define UART_SR_TACTIVE 0x00000800
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#define UART_SR_FDELT 0x00001000
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#define UART_CR_RXRST 0x00000001
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#define UART_CR_TXRST 0x00000002
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#define UART_CR_RX_EN 0x00000004
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#define UART_CR_RX_DIS 0x00000008
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#define UART_CR_TX_EN 0x00000010
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#define UART_CR_TX_DIS 0x00000020
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#define UART_CR_RST_TO 0x00000040
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#define UART_CR_STARTBRK 0x00000080
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#define UART_CR_STOPBRK 0x00000100
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#define UART_MR_CLKS 0x00000001
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#define UART_MR_CHRL 0x00000006
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#define UART_MR_CHRL_SH 1
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#define UART_MR_PAR 0x00000038
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#define UART_MR_PAR_SH 3
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#define UART_MR_NBSTOP 0x000000C0
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#define UART_MR_NBSTOP_SH 6
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#define UART_MR_CHMODE 0x00000300
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#define UART_MR_CHMODE_SH 8
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#define UART_MR_UCLKEN 0x00000400
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#define UART_MR_IRMODE 0x00000800
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#define UART_DATA_BITS_6 (0x3 << UART_MR_CHRL_SH)
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#define UART_DATA_BITS_7 (0x2 << UART_MR_CHRL_SH)
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#define UART_PARITY_ODD (0x1 << UART_MR_PAR_SH)
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#define UART_PARITY_EVEN (0x0 << UART_MR_PAR_SH)
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#define UART_STOP_BITS_1 (0x3 << UART_MR_NBSTOP_SH)
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#define UART_STOP_BITS_2 (0x2 << UART_MR_NBSTOP_SH)
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#define NORMAL_MODE (0x0 << UART_MR_CHMODE_SH)
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#define ECHO_MODE (0x1 << UART_MR_CHMODE_SH)
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#define LOCAL_LOOPBACK (0x2 << UART_MR_CHMODE_SH)
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#define REMOTE_LOOPBACK (0x3 << UART_MR_CHMODE_SH)
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#define UART_INPUT_CLK 50000000
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#define R_CR (0x00/4)
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#define R_MR (0x04/4)
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#define R_IER (0x08/4)
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#define R_IDR (0x0C/4)
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#define R_IMR (0x10/4)
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#define R_CISR (0x14/4)
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#define R_BRGR (0x18/4)
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#define R_RTOR (0x1C/4)
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#define R_RTRIG (0x20/4)
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#define R_MCR (0x24/4)
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#define R_MSR (0x28/4)
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#define R_SR (0x2C/4)
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#define R_TX_RX (0x30/4)
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#define R_BDIV (0x34/4)
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#define R_FDEL (0x38/4)
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#define R_PMIN (0x3C/4)
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#define R_PWID (0x40/4)
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#define R_TTRIG (0x44/4)
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static void uart_update_status(CadenceUARTState *s)
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{
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s->r[R_SR] = 0;
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s->r[R_SR] |= s->rx_count == CADENCE_UART_RX_FIFO_SIZE ? UART_SR_INTR_RFUL
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: 0;
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s->r[R_SR] |= !s->rx_count ? UART_SR_INTR_REMPTY : 0;
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s->r[R_SR] |= s->rx_count >= s->r[R_RTRIG] ? UART_SR_INTR_RTRIG : 0;
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s->r[R_SR] |= s->tx_count == CADENCE_UART_TX_FIFO_SIZE ? UART_SR_INTR_TFUL
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: 0;
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s->r[R_SR] |= !s->tx_count ? UART_SR_INTR_TEMPTY : 0;
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s->r[R_SR] |= s->tx_count >= s->r[R_TTRIG] ? UART_SR_TTRIG : 0;
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s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK;
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s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0;
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qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR]));
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}
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static void fifo_trigger_update(void *opaque)
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{
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CadenceUARTState *s = opaque;
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if (s->r[R_RTOR]) {
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s->r[R_CISR] |= UART_INTR_TIMEOUT;
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uart_update_status(s);
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}
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}
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static void uart_rx_reset(CadenceUARTState *s)
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{
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s->rx_wpos = 0;
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s->rx_count = 0;
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qemu_chr_fe_accept_input(&s->chr);
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}
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static void uart_tx_reset(CadenceUARTState *s)
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{
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s->tx_count = 0;
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}
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static void uart_send_breaks(CadenceUARTState *s)
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{
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int break_enabled = 1;
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qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
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&break_enabled);
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}
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static void uart_parameters_setup(CadenceUARTState *s)
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{
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QEMUSerialSetParams ssp;
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unsigned int baud_rate, packet_size;
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baud_rate = (s->r[R_MR] & UART_MR_CLKS) ?
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UART_INPUT_CLK / 8 : UART_INPUT_CLK;
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ssp.speed = baud_rate / (s->r[R_BRGR] * (s->r[R_BDIV] + 1));
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packet_size = 1;
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switch (s->r[R_MR] & UART_MR_PAR) {
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case UART_PARITY_EVEN:
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ssp.parity = 'E';
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packet_size++;
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break;
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case UART_PARITY_ODD:
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ssp.parity = 'O';
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packet_size++;
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break;
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default:
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ssp.parity = 'N';
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break;
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}
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switch (s->r[R_MR] & UART_MR_CHRL) {
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case UART_DATA_BITS_6:
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ssp.data_bits = 6;
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break;
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case UART_DATA_BITS_7:
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ssp.data_bits = 7;
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break;
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default:
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ssp.data_bits = 8;
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break;
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}
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switch (s->r[R_MR] & UART_MR_NBSTOP) {
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case UART_STOP_BITS_1:
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ssp.stop_bits = 1;
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break;
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default:
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ssp.stop_bits = 2;
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break;
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}
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packet_size += ssp.data_bits + ssp.stop_bits;
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s->char_tx_time = (NANOSECONDS_PER_SECOND / ssp.speed) * packet_size;
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qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
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}
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static int uart_can_receive(void *opaque)
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{
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CadenceUARTState *s = opaque;
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int ret = MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE);
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uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
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if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
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ret = MIN(ret, CADENCE_UART_RX_FIFO_SIZE - s->rx_count);
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}
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if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) {
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ret = MIN(ret, CADENCE_UART_TX_FIFO_SIZE - s->tx_count);
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}
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return ret;
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}
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static void uart_ctrl_update(CadenceUARTState *s)
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{
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if (s->r[R_CR] & UART_CR_TXRST) {
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uart_tx_reset(s);
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}
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if (s->r[R_CR] & UART_CR_RXRST) {
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uart_rx_reset(s);
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}
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s->r[R_CR] &= ~(UART_CR_TXRST | UART_CR_RXRST);
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if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) {
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uart_send_breaks(s);
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}
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}
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static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size)
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{
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CadenceUARTState *s = opaque;
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uint64_t new_rx_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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int i;
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if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
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return;
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}
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if (s->rx_count == CADENCE_UART_RX_FIFO_SIZE) {
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s->r[R_CISR] |= UART_INTR_ROVR;
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} else {
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for (i = 0; i < size; i++) {
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s->rx_fifo[s->rx_wpos] = buf[i];
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s->rx_wpos = (s->rx_wpos + 1) % CADENCE_UART_RX_FIFO_SIZE;
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s->rx_count++;
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}
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timer_mod(s->fifo_trigger_handle, new_rx_time +
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(s->char_tx_time * 4));
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}
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uart_update_status(s);
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}
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static gboolean cadence_uart_xmit(GIOChannel *chan, GIOCondition cond,
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void *opaque)
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{
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CadenceUARTState *s = opaque;
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int ret;
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/* instant drain the fifo when there's no back-end */
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if (!qemu_chr_fe_get_driver(&s->chr)) {
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s->tx_count = 0;
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return FALSE;
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}
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if (!s->tx_count) {
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return FALSE;
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}
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ret = qemu_chr_fe_write(&s->chr, s->tx_fifo, s->tx_count);
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if (ret >= 0) {
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s->tx_count -= ret;
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memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_count);
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}
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if (s->tx_count) {
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guint r = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
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cadence_uart_xmit, s);
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if (!r) {
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s->tx_count = 0;
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return FALSE;
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}
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}
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uart_update_status(s);
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return FALSE;
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}
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static void uart_write_tx_fifo(CadenceUARTState *s, const uint8_t *buf,
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int size)
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{
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if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) {
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return;
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}
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if (size > CADENCE_UART_TX_FIFO_SIZE - s->tx_count) {
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size = CADENCE_UART_TX_FIFO_SIZE - s->tx_count;
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/*
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* This can only be a guest error via a bad tx fifo register push,
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* as can_receive() should stop remote loop and echo modes ever getting
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* us to here.
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*/
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qemu_log_mask(LOG_GUEST_ERROR, "cadence_uart: TxFIFO overflow");
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s->r[R_CISR] |= UART_INTR_ROVR;
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}
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memcpy(s->tx_fifo + s->tx_count, buf, size);
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s->tx_count += size;
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cadence_uart_xmit(NULL, G_IO_OUT, s);
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}
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static void uart_receive(void *opaque, const uint8_t *buf, int size)
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{
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CadenceUARTState *s = opaque;
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uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
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if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
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uart_write_rx_fifo(opaque, buf, size);
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}
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if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) {
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uart_write_tx_fifo(s, buf, size);
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}
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}
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static void uart_event(void *opaque, int event)
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{
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CadenceUARTState *s = opaque;
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uint8_t buf = '\0';
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if (event == CHR_EVENT_BREAK) {
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uart_write_rx_fifo(opaque, &buf, 1);
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}
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uart_update_status(s);
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}
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static void uart_read_rx_fifo(CadenceUARTState *s, uint32_t *c)
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{
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if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
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return;
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}
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if (s->rx_count) {
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uint32_t rx_rpos = (CADENCE_UART_RX_FIFO_SIZE + s->rx_wpos -
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s->rx_count) % CADENCE_UART_RX_FIFO_SIZE;
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*c = s->rx_fifo[rx_rpos];
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s->rx_count--;
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qemu_chr_fe_accept_input(&s->chr);
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} else {
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*c = 0;
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}
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uart_update_status(s);
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}
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static void uart_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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CadenceUARTState *s = opaque;
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DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value);
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offset >>= 2;
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if (offset >= CADENCE_UART_R_MAX) {
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return;
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}
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switch (offset) {
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case R_IER: /* ier (wts imr) */
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s->r[R_IMR] |= value;
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break;
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case R_IDR: /* idr (wtc imr) */
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s->r[R_IMR] &= ~value;
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break;
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case R_IMR: /* imr (read only) */
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break;
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case R_CISR: /* cisr (wtc) */
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s->r[R_CISR] &= ~value;
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break;
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case R_TX_RX: /* UARTDR */
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switch (s->r[R_MR] & UART_MR_CHMODE) {
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case NORMAL_MODE:
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uart_write_tx_fifo(s, (uint8_t *) &value, 1);
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break;
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case LOCAL_LOOPBACK:
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uart_write_rx_fifo(opaque, (uint8_t *) &value, 1);
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break;
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}
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break;
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case R_BRGR: /* Baud rate generator */
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if (value >= 0x01) {
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s->r[offset] = value & 0xFFFF;
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}
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break;
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case R_BDIV: /* Baud rate divider */
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if (value >= 0x04) {
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s->r[offset] = value & 0xFF;
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}
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break;
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default:
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s->r[offset] = value;
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}
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switch (offset) {
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case R_CR:
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uart_ctrl_update(s);
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break;
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case R_MR:
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uart_parameters_setup(s);
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break;
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}
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uart_update_status(s);
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}
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static uint64_t uart_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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CadenceUARTState *s = opaque;
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uint32_t c = 0;
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offset >>= 2;
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if (offset >= CADENCE_UART_R_MAX) {
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c = 0;
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} else if (offset == R_TX_RX) {
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uart_read_rx_fifo(s, &c);
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} else {
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c = s->r[offset];
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}
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DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2), (unsigned)c);
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return c;
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}
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static const MemoryRegionOps uart_ops = {
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.read = uart_read,
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.write = uart_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
|
|
};
|
|
|
|
static void cadence_uart_reset(DeviceState *dev)
|
|
{
|
|
CadenceUARTState *s = CADENCE_UART(dev);
|
|
|
|
s->r[R_CR] = 0x00000128;
|
|
s->r[R_IMR] = 0;
|
|
s->r[R_CISR] = 0;
|
|
s->r[R_RTRIG] = 0x00000020;
|
|
s->r[R_BRGR] = 0x0000028B;
|
|
s->r[R_BDIV] = 0x0000000F;
|
|
s->r[R_TTRIG] = 0x00000020;
|
|
|
|
uart_rx_reset(s);
|
|
uart_tx_reset(s);
|
|
|
|
uart_update_status(s);
|
|
}
|
|
|
|
static void cadence_uart_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
CadenceUARTState *s = CADENCE_UART(dev);
|
|
|
|
s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,
|
|
fifo_trigger_update, s);
|
|
|
|
qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive,
|
|
uart_event, s, NULL, true);
|
|
}
|
|
|
|
static void cadence_uart_init(Object *obj)
|
|
{
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
|
|
CadenceUARTState *s = CADENCE_UART(obj);
|
|
|
|
memory_region_init_io(&s->iomem, obj, &uart_ops, s, "uart", 0x1000);
|
|
sysbus_init_mmio(sbd, &s->iomem);
|
|
sysbus_init_irq(sbd, &s->irq);
|
|
|
|
s->char_tx_time = (NANOSECONDS_PER_SECOND / 9600) * 10;
|
|
}
|
|
|
|
static int cadence_uart_post_load(void *opaque, int version_id)
|
|
{
|
|
CadenceUARTState *s = opaque;
|
|
|
|
/* Ensure these two aren't invalid numbers */
|
|
if (s->r[R_BRGR] < 1 || s->r[R_BRGR] & ~0xFFFF ||
|
|
s->r[R_BDIV] <= 3 || s->r[R_BDIV] & ~0xFF) {
|
|
/* Value is invalid, abort */
|
|
return 1;
|
|
}
|
|
|
|
uart_parameters_setup(s);
|
|
uart_update_status(s);
|
|
return 0;
|
|
}
|
|
|
|
static const VMStateDescription vmstate_cadence_uart = {
|
|
.name = "cadence_uart",
|
|
.version_id = 2,
|
|
.minimum_version_id = 2,
|
|
.post_load = cadence_uart_post_load,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT32_ARRAY(r, CadenceUARTState, CADENCE_UART_R_MAX),
|
|
VMSTATE_UINT8_ARRAY(rx_fifo, CadenceUARTState,
|
|
CADENCE_UART_RX_FIFO_SIZE),
|
|
VMSTATE_UINT8_ARRAY(tx_fifo, CadenceUARTState,
|
|
CADENCE_UART_TX_FIFO_SIZE),
|
|
VMSTATE_UINT32(rx_count, CadenceUARTState),
|
|
VMSTATE_UINT32(tx_count, CadenceUARTState),
|
|
VMSTATE_UINT32(rx_wpos, CadenceUARTState),
|
|
VMSTATE_TIMER_PTR(fifo_trigger_handle, CadenceUARTState),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static Property cadence_uart_properties[] = {
|
|
DEFINE_PROP_CHR("chardev", CadenceUARTState, chr),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void cadence_uart_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->realize = cadence_uart_realize;
|
|
dc->vmsd = &vmstate_cadence_uart;
|
|
dc->reset = cadence_uart_reset;
|
|
dc->props = cadence_uart_properties;
|
|
}
|
|
|
|
static const TypeInfo cadence_uart_info = {
|
|
.name = TYPE_CADENCE_UART,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(CadenceUARTState),
|
|
.instance_init = cadence_uart_init,
|
|
.class_init = cadence_uart_class_init,
|
|
};
|
|
|
|
static void cadence_uart_register_types(void)
|
|
{
|
|
type_register_static(&cadence_uart_info);
|
|
}
|
|
|
|
type_init(cadence_uart_register_types)
|