* target/arm: generate a custom MIDR for -cpu max * hw/misc/zynq_slcr: refactor to use standard register definition * Set ENET_BD_BDU in I.MX FEC controller * target/arm: Fix routing of singlestep exceptions * refactor a32/t32 decoder handling of PC * minor optimisations/cleanups of some a32/t32 codegen * target/arm/cpu64: Ensure kvm really supports aarch64=off * target/arm/cpu: Ensure we can use the pmu with kvm * target/arm: Minor cleanups preparatory to KVM SVE support -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAl1WrIsZHHBldGVyLm1h eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3tJ/D/9I0ccyciHwuekySUHs+Wq6 2grX8t6RFzlhA1ULoAaEO4x8uWWGnbiGTeSGM819T3nj1a7neQV12Xe5RRGG0j7n aeVseYnZF96oshKPkDSVTcGQisVfmmHIJ0oqx2k1aUGrmyFJlTuLWQBZCCiZKhxA zA6YzUbOA2apfi9nun6SbbjysiRD2lp2i9vI79nVlo+ca77v/1sdFUwzg0hRE//X IondHeWtCZScmc/GwABv4EdNzQ4Aerfe10v/pOKXEC59rPwEiaiSGBPu6SRUaGWH qHlwjVU2+BFGkz9Oy/7+tDTBk6saPi4taZF8SxxiC/QTyNV2ijyKV5iy9KOYAFw7 E41fhv4+Kch569/SX7fiyAxL0gAS2HGFtegByuQEgjjioOCRugFcX275NXvuW06j jfOP/zSD9P39WA0jCJaNj5FdJTcLmIuFxKjBUEX3Cdb+3igIq1BW0ZFd/OOBoo1W GHcEmO6tLyx35kigOb3TkayQpkqCoaGCcgzJ0g2Oy06rKwlcci+BfCfc3aG+uSSY +TuGjRhpQxQJJt880d7tBqeH9R5FABvQ0TEwGuACylDEZM5bN7BpZxCxCVN/bFG+ pzvzs/QtOq0FN7LK4L4rbuJui4nBhAyalbiIXQ8ihWQgmMqaYQSK8mXFgSZgizFl qATcYIr/q2gL4wHRos3XdA== =8BAF -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190816' into staging target-arm queue: * target/arm: generate a custom MIDR for -cpu max * hw/misc/zynq_slcr: refactor to use standard register definition * Set ENET_BD_BDU in I.MX FEC controller * target/arm: Fix routing of singlestep exceptions * refactor a32/t32 decoder handling of PC * minor optimisations/cleanups of some a32/t32 codegen * target/arm/cpu64: Ensure kvm really supports aarch64=off * target/arm/cpu: Ensure we can use the pmu with kvm * target/arm: Minor cleanups preparatory to KVM SVE support # gpg: Signature made Fri 16 Aug 2019 14:15:55 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20190816: (29 commits) target/arm: Use tcg_gen_extrh_i64_i32 to extract the high word target/arm: Simplify SMMLA, SMMLAR, SMMLS, SMMLSR target/arm: Use tcg_gen_rotri_i32 for gen_swap_half target/arm: Use ror32 instead of open-coding the operation target/arm: Remove redundant shift tests target/arm: Use tcg_gen_deposit_i32 for PKHBT, PKHTB target/arm: Use tcg_gen_extract_i32 for shifter_out_im target/arm/kvm64: Move the get/put of fpsimd registers out target/arm/kvm64: Fix error returns target/arm/cpu: Use div-round-up to determine predicate register array size target/arm/helper: zcr: Add build bug next to value range assumption target/arm/cpu: Ensure we can use the pmu with kvm target/arm/cpu64: Ensure kvm really supports aarch64=off target/arm: Remove helper_double_saturate target/arm: Use unallocated_encoding for aarch32 target/arm: Remove offset argument to gen_exception_bkpt_insn target/arm: Replace offset with pc in gen_exception_internal_insn target/arm: Replace offset with pc in gen_exception_insn target/arm: Replace s->pc with s->base.pc_next target/arm: Remove redundant s->pc & ~1 ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
527 lines
18 KiB
C
527 lines
18 KiB
C
/*
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* QEMU AArch64 CPU
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*
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* Copyright (c) 2013 Linaro Ltd
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see
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* <http://www.gnu.org/licenses/gpl-2.0.html>
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "qemu/module.h"
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#if !defined(CONFIG_USER_ONLY)
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#include "hw/loader.h"
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#endif
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#include "sysemu/kvm.h"
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#include "kvm_arm.h"
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#include "qapi/visitor.h"
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static inline void set_feature(CPUARMState *env, int feature)
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{
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env->features |= 1ULL << feature;
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}
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static inline void unset_feature(CPUARMState *env, int feature)
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{
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env->features &= ~(1ULL << feature);
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}
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#ifndef CONFIG_USER_ONLY
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static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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ARMCPU *cpu = env_archcpu(env);
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/* Number of cores is in [25:24]; otherwise we RAZ */
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return (cpu->core_count - 1) << 24;
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}
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#endif
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static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
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#ifndef CONFIG_USER_ONLY
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{ .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
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.access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
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.writefn = arm_cp_write_ignore },
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{ .name = "L2CTLR",
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.cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
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.access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
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.writefn = arm_cp_write_ignore },
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#endif
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{ .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "L2ECTLR",
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.cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "CPUACTLR",
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.cp = 15, .opc1 = 0, .crm = 15,
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.access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
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{ .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "CPUECTLR",
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.cp = 15, .opc1 = 1, .crm = 15,
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.access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
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{ .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "CPUMERRSR",
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.cp = 15, .opc1 = 2, .crm = 15,
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.access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
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{ .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "L2MERRSR",
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.cp = 15, .opc1 = 3, .crm = 15,
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.access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
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REGINFO_SENTINEL
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};
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static void aarch64_a57_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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cpu->dtb_compatible = "arm,cortex-a57";
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set_feature(&cpu->env, ARM_FEATURE_V8);
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set_feature(&cpu->env, ARM_FEATURE_VFP4);
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set_feature(&cpu->env, ARM_FEATURE_NEON);
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set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
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set_feature(&cpu->env, ARM_FEATURE_AARCH64);
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set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
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set_feature(&cpu->env, ARM_FEATURE_EL2);
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set_feature(&cpu->env, ARM_FEATURE_EL3);
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set_feature(&cpu->env, ARM_FEATURE_PMU);
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cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
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cpu->midr = 0x411fd070;
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cpu->revidr = 0x00000000;
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cpu->reset_fpsid = 0x41034070;
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cpu->isar.mvfr0 = 0x10110222;
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cpu->isar.mvfr1 = 0x12111111;
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cpu->isar.mvfr2 = 0x00000043;
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cpu->ctr = 0x8444c004;
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cpu->reset_sctlr = 0x00c50838;
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cpu->id_pfr0 = 0x00000131;
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cpu->id_pfr1 = 0x00011011;
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cpu->id_dfr0 = 0x03010066;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x10101105;
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cpu->id_mmfr1 = 0x40000000;
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cpu->id_mmfr2 = 0x01260000;
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cpu->id_mmfr3 = 0x02102211;
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cpu->isar.id_isar0 = 0x02101110;
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cpu->isar.id_isar1 = 0x13112111;
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cpu->isar.id_isar2 = 0x21232042;
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cpu->isar.id_isar3 = 0x01112131;
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cpu->isar.id_isar4 = 0x00011142;
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cpu->isar.id_isar5 = 0x00011121;
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cpu->isar.id_isar6 = 0;
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cpu->isar.id_aa64pfr0 = 0x00002222;
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cpu->id_aa64dfr0 = 0x10305106;
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cpu->isar.id_aa64isar0 = 0x00011120;
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cpu->isar.id_aa64mmfr0 = 0x00001124;
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cpu->dbgdidr = 0x3516d000;
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cpu->clidr = 0x0a200023;
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cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
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cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
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cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
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cpu->dcz_blocksize = 4; /* 64 bytes */
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cpu->gic_num_lrs = 4;
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cpu->gic_vpribits = 5;
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cpu->gic_vprebits = 5;
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define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
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}
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static void aarch64_a53_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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cpu->dtb_compatible = "arm,cortex-a53";
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set_feature(&cpu->env, ARM_FEATURE_V8);
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set_feature(&cpu->env, ARM_FEATURE_VFP4);
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set_feature(&cpu->env, ARM_FEATURE_NEON);
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set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
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set_feature(&cpu->env, ARM_FEATURE_AARCH64);
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set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
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set_feature(&cpu->env, ARM_FEATURE_EL2);
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set_feature(&cpu->env, ARM_FEATURE_EL3);
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set_feature(&cpu->env, ARM_FEATURE_PMU);
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cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
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cpu->midr = 0x410fd034;
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cpu->revidr = 0x00000000;
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cpu->reset_fpsid = 0x41034070;
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cpu->isar.mvfr0 = 0x10110222;
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cpu->isar.mvfr1 = 0x12111111;
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cpu->isar.mvfr2 = 0x00000043;
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cpu->ctr = 0x84448004; /* L1Ip = VIPT */
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cpu->reset_sctlr = 0x00c50838;
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cpu->id_pfr0 = 0x00000131;
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cpu->id_pfr1 = 0x00011011;
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cpu->id_dfr0 = 0x03010066;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x10101105;
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cpu->id_mmfr1 = 0x40000000;
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cpu->id_mmfr2 = 0x01260000;
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cpu->id_mmfr3 = 0x02102211;
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cpu->isar.id_isar0 = 0x02101110;
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cpu->isar.id_isar1 = 0x13112111;
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cpu->isar.id_isar2 = 0x21232042;
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cpu->isar.id_isar3 = 0x01112131;
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cpu->isar.id_isar4 = 0x00011142;
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cpu->isar.id_isar5 = 0x00011121;
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cpu->isar.id_isar6 = 0;
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cpu->isar.id_aa64pfr0 = 0x00002222;
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cpu->id_aa64dfr0 = 0x10305106;
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cpu->isar.id_aa64isar0 = 0x00011120;
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cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
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cpu->dbgdidr = 0x3516d000;
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cpu->clidr = 0x0a200023;
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cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
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cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
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cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
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cpu->dcz_blocksize = 4; /* 64 bytes */
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cpu->gic_num_lrs = 4;
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cpu->gic_vpribits = 5;
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cpu->gic_vprebits = 5;
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define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
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}
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static void aarch64_a72_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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cpu->dtb_compatible = "arm,cortex-a72";
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set_feature(&cpu->env, ARM_FEATURE_V8);
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set_feature(&cpu->env, ARM_FEATURE_VFP4);
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set_feature(&cpu->env, ARM_FEATURE_NEON);
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set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
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set_feature(&cpu->env, ARM_FEATURE_AARCH64);
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set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
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set_feature(&cpu->env, ARM_FEATURE_EL2);
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set_feature(&cpu->env, ARM_FEATURE_EL3);
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set_feature(&cpu->env, ARM_FEATURE_PMU);
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cpu->midr = 0x410fd083;
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cpu->revidr = 0x00000000;
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cpu->reset_fpsid = 0x41034080;
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cpu->isar.mvfr0 = 0x10110222;
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cpu->isar.mvfr1 = 0x12111111;
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cpu->isar.mvfr2 = 0x00000043;
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cpu->ctr = 0x8444c004;
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cpu->reset_sctlr = 0x00c50838;
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cpu->id_pfr0 = 0x00000131;
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cpu->id_pfr1 = 0x00011011;
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cpu->id_dfr0 = 0x03010066;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x10201105;
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cpu->id_mmfr1 = 0x40000000;
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cpu->id_mmfr2 = 0x01260000;
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cpu->id_mmfr3 = 0x02102211;
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cpu->isar.id_isar0 = 0x02101110;
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cpu->isar.id_isar1 = 0x13112111;
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cpu->isar.id_isar2 = 0x21232042;
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cpu->isar.id_isar3 = 0x01112131;
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cpu->isar.id_isar4 = 0x00011142;
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cpu->isar.id_isar5 = 0x00011121;
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cpu->isar.id_aa64pfr0 = 0x00002222;
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cpu->id_aa64dfr0 = 0x10305106;
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cpu->isar.id_aa64isar0 = 0x00011120;
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cpu->isar.id_aa64mmfr0 = 0x00001124;
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cpu->dbgdidr = 0x3516d000;
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cpu->clidr = 0x0a200023;
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cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
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cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
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cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
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cpu->dcz_blocksize = 4; /* 64 bytes */
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cpu->gic_num_lrs = 4;
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cpu->gic_vpribits = 5;
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cpu->gic_vprebits = 5;
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define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
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}
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static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name,
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void *opaque, Error **errp)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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visit_type_uint32(v, name, &cpu->sve_max_vq, errp);
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}
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static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name,
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void *opaque, Error **errp)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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Error *err = NULL;
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visit_type_uint32(v, name, &cpu->sve_max_vq, &err);
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if (!err && (cpu->sve_max_vq == 0 || cpu->sve_max_vq > ARM_MAX_VQ)) {
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error_setg(&err, "unsupported SVE vector length");
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error_append_hint(&err, "Valid sve-max-vq in range [1-%d]\n",
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ARM_MAX_VQ);
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}
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error_propagate(errp, err);
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}
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/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
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* otherwise, a CPU with as many features enabled as our emulation supports.
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* The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
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* this only needs to handle 64 bits.
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*/
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static void aarch64_max_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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if (kvm_enabled()) {
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kvm_arm_set_cpu_features_from_host(cpu);
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} else {
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uint64_t t;
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uint32_t u;
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aarch64_a57_initfn(obj);
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/*
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* Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real
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* one and try to apply errata workarounds or use impdef features we
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* don't provide.
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* An IMPLEMENTER field of 0 means "reserved for software use";
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* ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers
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* to see which features are present";
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* the VARIANT, PARTNUM and REVISION fields are all implementation
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* defined and we choose to define PARTNUM just in case guest
|
|
* code needs to distinguish this QEMU CPU from other software
|
|
* implementations, though this shouldn't be needed.
|
|
*/
|
|
t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0);
|
|
t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf);
|
|
t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q');
|
|
t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0);
|
|
t = FIELD_DP64(t, MIDR_EL1, REVISION, 0);
|
|
cpu->midr = t;
|
|
|
|
t = cpu->isar.id_aa64isar0;
|
|
t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */
|
|
t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);
|
|
t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */
|
|
t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
|
|
t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);
|
|
t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);
|
|
t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);
|
|
t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
|
|
t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
|
|
t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
|
|
t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
|
|
t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */
|
|
t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);
|
|
cpu->isar.id_aa64isar0 = t;
|
|
|
|
t = cpu->isar.id_aa64isar1;
|
|
t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);
|
|
t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
|
|
t = FIELD_DP64(t, ID_AA64ISAR1, APA, 1); /* PAuth, architected only */
|
|
t = FIELD_DP64(t, ID_AA64ISAR1, API, 0);
|
|
t = FIELD_DP64(t, ID_AA64ISAR1, GPA, 1);
|
|
t = FIELD_DP64(t, ID_AA64ISAR1, GPI, 0);
|
|
t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
|
|
t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
|
|
t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
|
|
cpu->isar.id_aa64isar1 = t;
|
|
|
|
t = cpu->isar.id_aa64pfr0;
|
|
t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
|
|
t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);
|
|
t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
|
|
cpu->isar.id_aa64pfr0 = t;
|
|
|
|
t = cpu->isar.id_aa64pfr1;
|
|
t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
|
|
cpu->isar.id_aa64pfr1 = t;
|
|
|
|
t = cpu->isar.id_aa64mmfr1;
|
|
t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
|
|
t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
|
|
cpu->isar.id_aa64mmfr1 = t;
|
|
|
|
/* Replicate the same data to the 32-bit id registers. */
|
|
u = cpu->isar.id_isar5;
|
|
u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */
|
|
u = FIELD_DP32(u, ID_ISAR5, SHA1, 1);
|
|
u = FIELD_DP32(u, ID_ISAR5, SHA2, 1);
|
|
u = FIELD_DP32(u, ID_ISAR5, CRC32, 1);
|
|
u = FIELD_DP32(u, ID_ISAR5, RDM, 1);
|
|
u = FIELD_DP32(u, ID_ISAR5, VCMA, 1);
|
|
cpu->isar.id_isar5 = u;
|
|
|
|
u = cpu->isar.id_isar6;
|
|
u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
|
|
u = FIELD_DP32(u, ID_ISAR6, DP, 1);
|
|
u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
|
|
u = FIELD_DP32(u, ID_ISAR6, SB, 1);
|
|
u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
|
|
cpu->isar.id_isar6 = u;
|
|
|
|
/*
|
|
* FIXME: We do not yet support ARMv8.2-fp16 for AArch32 yet,
|
|
* so do not set MVFR1.FPHP. Strictly speaking this is not legal,
|
|
* but it is also not legal to enable SVE without support for FP16,
|
|
* and enabling SVE in system mode is more useful in the short term.
|
|
*/
|
|
|
|
#ifdef CONFIG_USER_ONLY
|
|
/* For usermode -cpu max we can use a larger and more efficient DCZ
|
|
* blocksize since we don't have to follow what the hardware does.
|
|
*/
|
|
cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
|
|
cpu->dcz_blocksize = 7; /* 512 bytes */
|
|
#endif
|
|
|
|
cpu->sve_max_vq = ARM_MAX_VQ;
|
|
object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_vq,
|
|
cpu_max_set_sve_vq, NULL, NULL, &error_fatal);
|
|
}
|
|
}
|
|
|
|
struct ARMCPUInfo {
|
|
const char *name;
|
|
void (*initfn)(Object *obj);
|
|
void (*class_init)(ObjectClass *oc, void *data);
|
|
};
|
|
|
|
static const ARMCPUInfo aarch64_cpus[] = {
|
|
{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },
|
|
{ .name = "cortex-a53", .initfn = aarch64_a53_initfn },
|
|
{ .name = "cortex-a72", .initfn = aarch64_a72_initfn },
|
|
{ .name = "max", .initfn = aarch64_max_initfn },
|
|
{ .name = NULL }
|
|
};
|
|
|
|
static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
|
|
return arm_feature(&cpu->env, ARM_FEATURE_AARCH64);
|
|
}
|
|
|
|
static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
|
|
/* At this time, this property is only allowed if KVM is enabled. This
|
|
* restriction allows us to avoid fixing up functionality that assumes a
|
|
* uniform execution state like do_interrupt.
|
|
*/
|
|
if (value == false) {
|
|
if (!kvm_enabled() || !kvm_arm_aarch32_supported(CPU(cpu))) {
|
|
error_setg(errp, "'aarch64' feature cannot be disabled "
|
|
"unless KVM is enabled and 32-bit EL1 "
|
|
"is supported");
|
|
return;
|
|
}
|
|
unset_feature(&cpu->env, ARM_FEATURE_AARCH64);
|
|
} else {
|
|
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
|
|
}
|
|
}
|
|
|
|
static void aarch64_cpu_initfn(Object *obj)
|
|
{
|
|
object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64,
|
|
aarch64_cpu_set_aarch64, NULL);
|
|
object_property_set_description(obj, "aarch64",
|
|
"Set on/off to enable/disable aarch64 "
|
|
"execution state ",
|
|
NULL);
|
|
}
|
|
|
|
static void aarch64_cpu_finalizefn(Object *obj)
|
|
{
|
|
}
|
|
|
|
static gchar *aarch64_gdb_arch_name(CPUState *cs)
|
|
{
|
|
return g_strdup("aarch64");
|
|
}
|
|
|
|
static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
CPUClass *cc = CPU_CLASS(oc);
|
|
|
|
cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
|
|
cc->gdb_read_register = aarch64_cpu_gdb_read_register;
|
|
cc->gdb_write_register = aarch64_cpu_gdb_write_register;
|
|
cc->gdb_num_core_regs = 34;
|
|
cc->gdb_core_xml_file = "aarch64-core.xml";
|
|
cc->gdb_arch_name = aarch64_gdb_arch_name;
|
|
}
|
|
|
|
static void aarch64_cpu_instance_init(Object *obj)
|
|
{
|
|
ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj);
|
|
|
|
acc->info->initfn(obj);
|
|
arm_cpu_post_init(obj);
|
|
}
|
|
|
|
static void cpu_register_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
ARMCPUClass *acc = ARM_CPU_CLASS(oc);
|
|
|
|
acc->info = data;
|
|
}
|
|
|
|
static void aarch64_cpu_register(const ARMCPUInfo *info)
|
|
{
|
|
TypeInfo type_info = {
|
|
.parent = TYPE_AARCH64_CPU,
|
|
.instance_size = sizeof(ARMCPU),
|
|
.instance_init = aarch64_cpu_instance_init,
|
|
.class_size = sizeof(ARMCPUClass),
|
|
.class_init = info->class_init ?: cpu_register_class_init,
|
|
.class_data = (void *)info,
|
|
};
|
|
|
|
type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
|
|
type_register(&type_info);
|
|
g_free((void *)type_info.name);
|
|
}
|
|
|
|
static const TypeInfo aarch64_cpu_type_info = {
|
|
.name = TYPE_AARCH64_CPU,
|
|
.parent = TYPE_ARM_CPU,
|
|
.instance_size = sizeof(ARMCPU),
|
|
.instance_init = aarch64_cpu_initfn,
|
|
.instance_finalize = aarch64_cpu_finalizefn,
|
|
.abstract = true,
|
|
.class_size = sizeof(AArch64CPUClass),
|
|
.class_init = aarch64_cpu_class_init,
|
|
};
|
|
|
|
static void aarch64_cpu_register_types(void)
|
|
{
|
|
const ARMCPUInfo *info = aarch64_cpus;
|
|
|
|
type_register_static(&aarch64_cpu_type_info);
|
|
|
|
while (info->name) {
|
|
aarch64_cpu_register(info);
|
|
info++;
|
|
}
|
|
}
|
|
|
|
type_init(aarch64_cpu_register_types)
|