Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6530 c046a42c-6fe2-441c-8c8c-71466251a162
634 lines
17 KiB
C
634 lines
17 KiB
C
/*
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* QEMU KVM support
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*
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* Copyright (C) 2006-2008 Qumranet Technologies
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* Copyright IBM, Corp. 2008
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*
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* Authors:
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* Anthony Liguori <aliguori@us.ibm.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#include <sys/types.h>
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#include <sys/ioctl.h>
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#include <sys/mman.h>
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#include <linux/kvm.h>
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#include "qemu-common.h"
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#include "sysemu.h"
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#include "kvm.h"
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#include "cpu.h"
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//#define DEBUG_KVM
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#ifdef DEBUG_KVM
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#define dprintf(fmt, ...) \
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do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
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#else
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#define dprintf(fmt, ...) \
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do { } while (0)
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#endif
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int kvm_arch_init_vcpu(CPUState *env)
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{
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struct {
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struct kvm_cpuid cpuid;
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struct kvm_cpuid_entry entries[100];
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} __attribute__((packed)) cpuid_data;
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uint32_t limit, i, cpuid_i;
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uint32_t eax, ebx, ecx, edx;
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cpuid_i = 0;
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cpu_x86_cpuid(env, 0, &eax, &ebx, &ecx, &edx);
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limit = eax;
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for (i = 0; i <= limit; i++) {
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struct kvm_cpuid_entry *c = &cpuid_data.entries[cpuid_i++];
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cpu_x86_cpuid(env, i, &eax, &ebx, &ecx, &edx);
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c->function = i;
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c->eax = eax;
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c->ebx = ebx;
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c->ecx = ecx;
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c->edx = edx;
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}
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cpu_x86_cpuid(env, 0x80000000, &eax, &ebx, &ecx, &edx);
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limit = eax;
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for (i = 0x80000000; i <= limit; i++) {
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struct kvm_cpuid_entry *c = &cpuid_data.entries[cpuid_i++];
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cpu_x86_cpuid(env, i, &eax, &ebx, &ecx, &edx);
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c->function = i;
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c->eax = eax;
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c->ebx = ebx;
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c->ecx = ecx;
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c->edx = edx;
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}
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cpuid_data.cpuid.nent = cpuid_i;
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return kvm_vcpu_ioctl(env, KVM_SET_CPUID, &cpuid_data);
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}
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static int kvm_has_msr_star(CPUState *env)
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{
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static int has_msr_star;
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int ret;
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/* first time */
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if (has_msr_star == 0) {
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struct kvm_msr_list msr_list, *kvm_msr_list;
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has_msr_star = -1;
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/* Obtain MSR list from KVM. These are the MSRs that we must
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* save/restore */
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msr_list.nmsrs = 0;
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ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
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if (ret < 0)
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return 0;
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kvm_msr_list = qemu_mallocz(sizeof(msr_list) +
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msr_list.nmsrs * sizeof(msr_list.indices[0]));
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kvm_msr_list->nmsrs = msr_list.nmsrs;
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ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
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if (ret >= 0) {
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int i;
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for (i = 0; i < kvm_msr_list->nmsrs; i++) {
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if (kvm_msr_list->indices[i] == MSR_STAR) {
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has_msr_star = 1;
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break;
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}
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}
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}
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free(kvm_msr_list);
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}
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if (has_msr_star == 1)
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return 1;
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return 0;
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}
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int kvm_arch_init(KVMState *s, int smp_cpus)
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{
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int ret;
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/* create vm86 tss. KVM uses vm86 mode to emulate 16-bit code
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* directly. In order to use vm86 mode, a TSS is needed. Since this
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* must be part of guest physical memory, we need to allocate it. Older
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* versions of KVM just assumed that it would be at the end of physical
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* memory but that doesn't work with more than 4GB of memory. We simply
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* refuse to work with those older versions of KVM. */
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ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
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if (ret <= 0) {
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fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
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return ret;
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}
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/* this address is 3 pages before the bios, and the bios should present
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* as unavaible memory. FIXME, need to ensure the e820 map deals with
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* this?
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*/
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return kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
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}
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static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
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{
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lhs->selector = rhs->selector;
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lhs->base = rhs->base;
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lhs->limit = rhs->limit;
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lhs->type = 3;
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lhs->present = 1;
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lhs->dpl = 3;
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lhs->db = 0;
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lhs->s = 1;
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lhs->l = 0;
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lhs->g = 0;
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lhs->avl = 0;
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lhs->unusable = 0;
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}
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static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
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{
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unsigned flags = rhs->flags;
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lhs->selector = rhs->selector;
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lhs->base = rhs->base;
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lhs->limit = rhs->limit;
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lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
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lhs->present = (flags & DESC_P_MASK) != 0;
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lhs->dpl = rhs->selector & 3;
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lhs->db = (flags >> DESC_B_SHIFT) & 1;
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lhs->s = (flags & DESC_S_MASK) != 0;
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lhs->l = (flags >> DESC_L_SHIFT) & 1;
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lhs->g = (flags & DESC_G_MASK) != 0;
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lhs->avl = (flags & DESC_AVL_MASK) != 0;
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lhs->unusable = 0;
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}
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static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
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{
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lhs->selector = rhs->selector;
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lhs->base = rhs->base;
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lhs->limit = rhs->limit;
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lhs->flags =
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(rhs->type << DESC_TYPE_SHIFT)
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| (rhs->present * DESC_P_MASK)
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| (rhs->dpl << DESC_DPL_SHIFT)
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| (rhs->db << DESC_B_SHIFT)
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| (rhs->s * DESC_S_MASK)
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| (rhs->l << DESC_L_SHIFT)
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| (rhs->g * DESC_G_MASK)
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| (rhs->avl * DESC_AVL_MASK);
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}
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static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
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{
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if (set)
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*kvm_reg = *qemu_reg;
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else
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*qemu_reg = *kvm_reg;
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}
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static int kvm_getput_regs(CPUState *env, int set)
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{
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struct kvm_regs regs;
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int ret = 0;
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if (!set) {
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ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s);
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if (ret < 0)
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return ret;
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}
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kvm_getput_reg(®s.rax, &env->regs[R_EAX], set);
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kvm_getput_reg(®s.rbx, &env->regs[R_EBX], set);
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kvm_getput_reg(®s.rcx, &env->regs[R_ECX], set);
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kvm_getput_reg(®s.rdx, &env->regs[R_EDX], set);
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kvm_getput_reg(®s.rsi, &env->regs[R_ESI], set);
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kvm_getput_reg(®s.rdi, &env->regs[R_EDI], set);
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kvm_getput_reg(®s.rsp, &env->regs[R_ESP], set);
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kvm_getput_reg(®s.rbp, &env->regs[R_EBP], set);
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#ifdef TARGET_X86_64
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kvm_getput_reg(®s.r8, &env->regs[8], set);
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kvm_getput_reg(®s.r9, &env->regs[9], set);
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kvm_getput_reg(®s.r10, &env->regs[10], set);
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kvm_getput_reg(®s.r11, &env->regs[11], set);
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kvm_getput_reg(®s.r12, &env->regs[12], set);
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kvm_getput_reg(®s.r13, &env->regs[13], set);
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kvm_getput_reg(®s.r14, &env->regs[14], set);
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kvm_getput_reg(®s.r15, &env->regs[15], set);
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#endif
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kvm_getput_reg(®s.rflags, &env->eflags, set);
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kvm_getput_reg(®s.rip, &env->eip, set);
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if (set)
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ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, ®s);
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return ret;
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}
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static int kvm_put_fpu(CPUState *env)
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{
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struct kvm_fpu fpu;
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int i;
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memset(&fpu, 0, sizeof fpu);
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fpu.fsw = env->fpus & ~(7 << 11);
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fpu.fsw |= (env->fpstt & 7) << 11;
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fpu.fcw = env->fpuc;
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for (i = 0; i < 8; ++i)
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fpu.ftwx |= (!env->fptags[i]) << i;
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memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
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memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
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fpu.mxcsr = env->mxcsr;
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return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
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}
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static int kvm_put_sregs(CPUState *env)
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{
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struct kvm_sregs sregs;
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memcpy(sregs.interrupt_bitmap,
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env->interrupt_bitmap,
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sizeof(sregs.interrupt_bitmap));
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if ((env->eflags & VM_MASK)) {
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set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
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set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
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set_v8086_seg(&sregs.es, &env->segs[R_ES]);
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set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
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set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
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set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
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} else {
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set_seg(&sregs.cs, &env->segs[R_CS]);
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set_seg(&sregs.ds, &env->segs[R_DS]);
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set_seg(&sregs.es, &env->segs[R_ES]);
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set_seg(&sregs.fs, &env->segs[R_FS]);
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set_seg(&sregs.gs, &env->segs[R_GS]);
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set_seg(&sregs.ss, &env->segs[R_SS]);
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if (env->cr[0] & CR0_PE_MASK) {
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/* force ss cpl to cs cpl */
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sregs.ss.selector = (sregs.ss.selector & ~3) |
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(sregs.cs.selector & 3);
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sregs.ss.dpl = sregs.ss.selector & 3;
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}
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}
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set_seg(&sregs.tr, &env->tr);
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set_seg(&sregs.ldt, &env->ldt);
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sregs.idt.limit = env->idt.limit;
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sregs.idt.base = env->idt.base;
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sregs.gdt.limit = env->gdt.limit;
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sregs.gdt.base = env->gdt.base;
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sregs.cr0 = env->cr[0];
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sregs.cr2 = env->cr[2];
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sregs.cr3 = env->cr[3];
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sregs.cr4 = env->cr[4];
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sregs.cr8 = cpu_get_apic_tpr(env);
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sregs.apic_base = cpu_get_apic_base(env);
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sregs.efer = env->efer;
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return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
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}
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static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
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uint32_t index, uint64_t value)
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{
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entry->index = index;
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entry->data = value;
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}
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static int kvm_put_msrs(CPUState *env)
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{
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struct {
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struct kvm_msrs info;
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struct kvm_msr_entry entries[100];
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} msr_data;
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struct kvm_msr_entry *msrs = msr_data.entries;
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int n = 0;
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kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
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kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
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kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
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if (kvm_has_msr_star(env))
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kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
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kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
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#ifdef TARGET_X86_64
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/* FIXME if lm capable */
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kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
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kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
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kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
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kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
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#endif
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msr_data.info.nmsrs = n;
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return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
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}
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static int kvm_get_fpu(CPUState *env)
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{
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struct kvm_fpu fpu;
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int i, ret;
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ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
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if (ret < 0)
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return ret;
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env->fpstt = (fpu.fsw >> 11) & 7;
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env->fpus = fpu.fsw;
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env->fpuc = fpu.fcw;
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for (i = 0; i < 8; ++i)
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env->fptags[i] = !((fpu.ftwx >> i) & 1);
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memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
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memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
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env->mxcsr = fpu.mxcsr;
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return 0;
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}
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static int kvm_get_sregs(CPUState *env)
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{
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struct kvm_sregs sregs;
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uint32_t hflags;
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int ret;
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ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
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if (ret < 0)
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return ret;
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memcpy(env->interrupt_bitmap,
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sregs.interrupt_bitmap,
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sizeof(sregs.interrupt_bitmap));
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get_seg(&env->segs[R_CS], &sregs.cs);
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get_seg(&env->segs[R_DS], &sregs.ds);
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get_seg(&env->segs[R_ES], &sregs.es);
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get_seg(&env->segs[R_FS], &sregs.fs);
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get_seg(&env->segs[R_GS], &sregs.gs);
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get_seg(&env->segs[R_SS], &sregs.ss);
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get_seg(&env->tr, &sregs.tr);
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get_seg(&env->ldt, &sregs.ldt);
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env->idt.limit = sregs.idt.limit;
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env->idt.base = sregs.idt.base;
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env->gdt.limit = sregs.gdt.limit;
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env->gdt.base = sregs.gdt.base;
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env->cr[0] = sregs.cr0;
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env->cr[2] = sregs.cr2;
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env->cr[3] = sregs.cr3;
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env->cr[4] = sregs.cr4;
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cpu_set_apic_base(env, sregs.apic_base);
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env->efer = sregs.efer;
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//cpu_set_apic_tpr(env, sregs.cr8);
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#define HFLAG_COPY_MASK ~( \
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HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
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HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
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HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
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HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
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hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
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hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
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hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
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(HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
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hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
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hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
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(HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
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if (env->efer & MSR_EFER_LMA) {
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hflags |= HF_LMA_MASK;
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}
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if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
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hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
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} else {
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hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
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(DESC_B_SHIFT - HF_CS32_SHIFT);
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hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
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(DESC_B_SHIFT - HF_SS32_SHIFT);
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if (!(env->cr[0] & CR0_PE_MASK) ||
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(env->eflags & VM_MASK) ||
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!(hflags & HF_CS32_MASK)) {
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hflags |= HF_ADDSEG_MASK;
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} else {
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hflags |= ((env->segs[R_DS].base |
|
|
env->segs[R_ES].base |
|
|
env->segs[R_SS].base) != 0) <<
|
|
HF_ADDSEG_SHIFT;
|
|
}
|
|
}
|
|
env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int kvm_get_msrs(CPUState *env)
|
|
{
|
|
struct {
|
|
struct kvm_msrs info;
|
|
struct kvm_msr_entry entries[100];
|
|
} msr_data;
|
|
struct kvm_msr_entry *msrs = msr_data.entries;
|
|
int ret, i, n;
|
|
|
|
n = 0;
|
|
msrs[n++].index = MSR_IA32_SYSENTER_CS;
|
|
msrs[n++].index = MSR_IA32_SYSENTER_ESP;
|
|
msrs[n++].index = MSR_IA32_SYSENTER_EIP;
|
|
if (kvm_has_msr_star(env))
|
|
msrs[n++].index = MSR_STAR;
|
|
msrs[n++].index = MSR_IA32_TSC;
|
|
#ifdef TARGET_X86_64
|
|
/* FIXME lm_capable_kernel */
|
|
msrs[n++].index = MSR_CSTAR;
|
|
msrs[n++].index = MSR_KERNELGSBASE;
|
|
msrs[n++].index = MSR_FMASK;
|
|
msrs[n++].index = MSR_LSTAR;
|
|
#endif
|
|
msr_data.info.nmsrs = n;
|
|
ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
for (i = 0; i < ret; i++) {
|
|
switch (msrs[i].index) {
|
|
case MSR_IA32_SYSENTER_CS:
|
|
env->sysenter_cs = msrs[i].data;
|
|
break;
|
|
case MSR_IA32_SYSENTER_ESP:
|
|
env->sysenter_esp = msrs[i].data;
|
|
break;
|
|
case MSR_IA32_SYSENTER_EIP:
|
|
env->sysenter_eip = msrs[i].data;
|
|
break;
|
|
case MSR_STAR:
|
|
env->star = msrs[i].data;
|
|
break;
|
|
#ifdef TARGET_X86_64
|
|
case MSR_CSTAR:
|
|
env->cstar = msrs[i].data;
|
|
break;
|
|
case MSR_KERNELGSBASE:
|
|
env->kernelgsbase = msrs[i].data;
|
|
break;
|
|
case MSR_FMASK:
|
|
env->fmask = msrs[i].data;
|
|
break;
|
|
case MSR_LSTAR:
|
|
env->lstar = msrs[i].data;
|
|
break;
|
|
#endif
|
|
case MSR_IA32_TSC:
|
|
env->tsc = msrs[i].data;
|
|
break;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int kvm_arch_put_registers(CPUState *env)
|
|
{
|
|
int ret;
|
|
|
|
ret = kvm_getput_regs(env, 1);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = kvm_put_fpu(env);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = kvm_put_sregs(env);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = kvm_put_msrs(env);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int kvm_arch_get_registers(CPUState *env)
|
|
{
|
|
int ret;
|
|
|
|
ret = kvm_getput_regs(env, 0);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = kvm_get_fpu(env);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = kvm_get_sregs(env);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = kvm_get_msrs(env);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
|
|
{
|
|
/* Try to inject an interrupt if the guest can accept it */
|
|
if (run->ready_for_interrupt_injection &&
|
|
(env->interrupt_request & CPU_INTERRUPT_HARD) &&
|
|
(env->eflags & IF_MASK)) {
|
|
int irq;
|
|
|
|
env->interrupt_request &= ~CPU_INTERRUPT_HARD;
|
|
irq = cpu_get_pic_interrupt(env);
|
|
if (irq >= 0) {
|
|
struct kvm_interrupt intr;
|
|
intr.irq = irq;
|
|
/* FIXME: errors */
|
|
dprintf("injected interrupt %d\n", irq);
|
|
kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
|
|
}
|
|
}
|
|
|
|
/* If we have an interrupt but the guest is not ready to receive an
|
|
* interrupt, request an interrupt window exit. This will
|
|
* cause a return to userspace as soon as the guest is ready to
|
|
* receive interrupts. */
|
|
if ((env->interrupt_request & CPU_INTERRUPT_HARD))
|
|
run->request_interrupt_window = 1;
|
|
else
|
|
run->request_interrupt_window = 0;
|
|
|
|
dprintf("setting tpr\n");
|
|
run->cr8 = cpu_get_apic_tpr(env);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
|
|
{
|
|
if (run->if_flag)
|
|
env->eflags |= IF_MASK;
|
|
else
|
|
env->eflags &= ~IF_MASK;
|
|
|
|
cpu_set_apic_tpr(env, run->cr8);
|
|
cpu_set_apic_base(env, run->apic_base);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int kvm_handle_halt(CPUState *env)
|
|
{
|
|
if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
|
|
(env->eflags & IF_MASK)) &&
|
|
!(env->interrupt_request & CPU_INTERRUPT_NMI)) {
|
|
env->halted = 1;
|
|
env->exception_index = EXCP_HLT;
|
|
return 0;
|
|
}
|
|
|
|
return 1;
|
|
}
|
|
|
|
int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
|
|
{
|
|
int ret = 0;
|
|
|
|
switch (run->exit_reason) {
|
|
case KVM_EXIT_HLT:
|
|
dprintf("handle_hlt\n");
|
|
ret = kvm_handle_halt(env);
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|