Model the PL111 CLCD controller. This is a minor variation on the PL110; the major programmer visible differences are support for hardware cursor (unimplemented) and two new pixel formats. Since syborg_fb.c borrows the pl11x pixel drawing routines, we also update it to cope with the new slightly larger array of function pointers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
481 lines
12 KiB
C
481 lines
12 KiB
C
/*
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* Arm PrimeCell PL110 Color LCD Controller
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*
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* Copyright (c) 2005-2009 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licensed under the GNU LGPL
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*/
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#include "sysbus.h"
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#include "console.h"
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#include "framebuffer.h"
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#define PL110_CR_EN 0x001
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#define PL110_CR_BGR 0x100
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#define PL110_CR_BEBO 0x200
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#define PL110_CR_BEPO 0x400
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#define PL110_CR_PWR 0x800
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enum pl110_bppmode
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{
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BPP_1,
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BPP_2,
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BPP_4,
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BPP_8,
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BPP_16,
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BPP_32,
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BPP_16_565, /* PL111 only */
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BPP_12 /* PL111 only */
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};
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/* The Versatile/PB uses a slightly modified PL110 controller. */
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enum pl110_version
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{
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PL110,
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PL110_VERSATILE,
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PL111
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};
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typedef struct {
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SysBusDevice busdev;
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DisplayState *ds;
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int version;
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uint32_t timing[4];
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uint32_t cr;
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uint32_t upbase;
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uint32_t lpbase;
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uint32_t int_status;
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uint32_t int_mask;
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int cols;
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int rows;
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enum pl110_bppmode bpp;
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int invalidate;
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uint32_t pallette[256];
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uint32_t raw_pallette[128];
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qemu_irq irq;
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} pl110_state;
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static const VMStateDescription vmstate_pl110 = {
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.name = "pl110",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_INT32(version, pl110_state),
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VMSTATE_UINT32_ARRAY(timing, pl110_state, 4),
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VMSTATE_UINT32(cr, pl110_state),
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VMSTATE_UINT32(upbase, pl110_state),
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VMSTATE_UINT32(lpbase, pl110_state),
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VMSTATE_UINT32(int_status, pl110_state),
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VMSTATE_UINT32(int_mask, pl110_state),
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VMSTATE_INT32(cols, pl110_state),
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VMSTATE_INT32(rows, pl110_state),
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VMSTATE_UINT32(bpp, pl110_state),
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VMSTATE_INT32(invalidate, pl110_state),
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VMSTATE_UINT32_ARRAY(pallette, pl110_state, 256),
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VMSTATE_UINT32_ARRAY(raw_pallette, pl110_state, 128),
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VMSTATE_END_OF_LIST()
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}
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};
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static const unsigned char pl110_id[] =
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{ 0x10, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
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/* The Arm documentation (DDI0224C) says the CLDC on the Versatile board
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has a different ID. However Linux only looks for the normal ID. */
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#if 0
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static const unsigned char pl110_versatile_id[] =
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{ 0x93, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
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#else
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#define pl110_versatile_id pl110_id
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#endif
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static const unsigned char pl111_id[] = {
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0x11, 0x11, 0x24, 0x00, 0x0d, 0xf0, 0x05, 0xb1
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};
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/* Indexed by pl110_version */
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static const unsigned char *idregs[] = {
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pl110_id,
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pl110_versatile_id,
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pl111_id
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};
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#include "pixel_ops.h"
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#define BITS 8
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#include "pl110_template.h"
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#define BITS 15
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#include "pl110_template.h"
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#define BITS 16
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#include "pl110_template.h"
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#define BITS 24
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#include "pl110_template.h"
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#define BITS 32
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#include "pl110_template.h"
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static int pl110_enabled(pl110_state *s)
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{
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return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR);
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}
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static void pl110_update_display(void *opaque)
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{
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pl110_state *s = (pl110_state *)opaque;
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drawfn* fntable;
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drawfn fn;
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int dest_width;
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int src_width;
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int bpp_offset;
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int first;
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int last;
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if (!pl110_enabled(s))
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return;
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switch (ds_get_bits_per_pixel(s->ds)) {
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case 0:
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return;
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case 8:
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fntable = pl110_draw_fn_8;
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dest_width = 1;
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break;
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case 15:
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fntable = pl110_draw_fn_15;
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dest_width = 2;
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break;
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case 16:
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fntable = pl110_draw_fn_16;
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dest_width = 2;
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break;
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case 24:
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fntable = pl110_draw_fn_24;
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dest_width = 3;
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break;
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case 32:
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fntable = pl110_draw_fn_32;
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dest_width = 4;
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break;
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default:
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fprintf(stderr, "pl110: Bad color depth\n");
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exit(1);
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}
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if (s->cr & PL110_CR_BGR)
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bpp_offset = 0;
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else
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bpp_offset = 24;
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if ((s->version != PL111) && (s->bpp == BPP_16)) {
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/* The PL110's native 16 bit mode is 5551; however
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* most boards with a PL110 implement an external
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* mux which allows bits to be reshuffled to give
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* 565 format. The mux is typically controlled by
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* an external system register.
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* This should be controlled by a GPIO input pin
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* so boards can wire it up to their register.
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* For now, force 16 bit to be 565, to match
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* previous QEMU PL110 model behaviour.
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*
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* The PL111 straightforwardly implements both
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* 5551 and 565 under control of the bpp field
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* in the LCDControl register.
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*/
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bpp_offset += (BPP_16_565 - BPP_16);
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}
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if (s->cr & PL110_CR_BEBO)
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fn = fntable[s->bpp + 8 + bpp_offset];
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else if (s->cr & PL110_CR_BEPO)
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fn = fntable[s->bpp + 16 + bpp_offset];
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else
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fn = fntable[s->bpp + bpp_offset];
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src_width = s->cols;
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switch (s->bpp) {
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case BPP_1:
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src_width >>= 3;
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break;
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case BPP_2:
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src_width >>= 2;
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break;
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case BPP_4:
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src_width >>= 1;
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break;
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case BPP_8:
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break;
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case BPP_16:
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case BPP_16_565:
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case BPP_12:
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src_width <<= 1;
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break;
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case BPP_32:
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src_width <<= 2;
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break;
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}
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dest_width *= s->cols;
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first = 0;
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framebuffer_update_display(s->ds,
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s->upbase, s->cols, s->rows,
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src_width, dest_width, 0,
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s->invalidate,
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fn, s->pallette,
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&first, &last);
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if (first >= 0) {
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dpy_update(s->ds, 0, first, s->cols, last - first + 1);
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}
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s->invalidate = 0;
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}
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static void pl110_invalidate_display(void * opaque)
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{
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pl110_state *s = (pl110_state *)opaque;
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s->invalidate = 1;
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if (pl110_enabled(s)) {
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qemu_console_resize(s->ds, s->cols, s->rows);
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}
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}
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static void pl110_update_pallette(pl110_state *s, int n)
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{
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int i;
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uint32_t raw;
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unsigned int r, g, b;
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raw = s->raw_pallette[n];
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n <<= 1;
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for (i = 0; i < 2; i++) {
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r = (raw & 0x1f) << 3;
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raw >>= 5;
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g = (raw & 0x1f) << 3;
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raw >>= 5;
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b = (raw & 0x1f) << 3;
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/* The I bit is ignored. */
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raw >>= 6;
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switch (ds_get_bits_per_pixel(s->ds)) {
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case 8:
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s->pallette[n] = rgb_to_pixel8(r, g, b);
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break;
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case 15:
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s->pallette[n] = rgb_to_pixel15(r, g, b);
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break;
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case 16:
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s->pallette[n] = rgb_to_pixel16(r, g, b);
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break;
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case 24:
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case 32:
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s->pallette[n] = rgb_to_pixel32(r, g, b);
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break;
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}
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n++;
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}
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}
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static void pl110_resize(pl110_state *s, int width, int height)
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{
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if (width != s->cols || height != s->rows) {
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if (pl110_enabled(s)) {
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qemu_console_resize(s->ds, width, height);
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}
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}
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s->cols = width;
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s->rows = height;
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}
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/* Update interrupts. */
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static void pl110_update(pl110_state *s)
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{
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/* TODO: Implement interrupts. */
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}
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static uint32_t pl110_read(void *opaque, target_phys_addr_t offset)
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{
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pl110_state *s = (pl110_state *)opaque;
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if (offset >= 0xfe0 && offset < 0x1000) {
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return idregs[s->version][(offset - 0xfe0) >> 2];
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}
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if (offset >= 0x200 && offset < 0x400) {
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return s->raw_pallette[(offset - 0x200) >> 2];
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}
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switch (offset >> 2) {
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case 0: /* LCDTiming0 */
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return s->timing[0];
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case 1: /* LCDTiming1 */
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return s->timing[1];
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case 2: /* LCDTiming2 */
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return s->timing[2];
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case 3: /* LCDTiming3 */
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return s->timing[3];
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case 4: /* LCDUPBASE */
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return s->upbase;
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case 5: /* LCDLPBASE */
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return s->lpbase;
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case 6: /* LCDIMSC */
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if (s->version != PL110) {
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return s->cr;
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}
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return s->int_mask;
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case 7: /* LCDControl */
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if (s->version != PL110) {
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return s->int_mask;
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}
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return s->cr;
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case 8: /* LCDRIS */
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return s->int_status;
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case 9: /* LCDMIS */
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return s->int_status & s->int_mask;
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case 11: /* LCDUPCURR */
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/* TODO: Implement vertical refresh. */
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return s->upbase;
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case 12: /* LCDLPCURR */
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return s->lpbase;
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default:
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hw_error("pl110_read: Bad offset %x\n", (int)offset);
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return 0;
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}
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}
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static void pl110_write(void *opaque, target_phys_addr_t offset,
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uint32_t val)
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{
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pl110_state *s = (pl110_state *)opaque;
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int n;
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/* For simplicity invalidate the display whenever a control register
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is writen to. */
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s->invalidate = 1;
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if (offset >= 0x200 && offset < 0x400) {
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/* Pallette. */
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n = (offset - 0x200) >> 2;
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s->raw_pallette[(offset - 0x200) >> 2] = val;
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pl110_update_pallette(s, n);
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return;
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}
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switch (offset >> 2) {
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case 0: /* LCDTiming0 */
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s->timing[0] = val;
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n = ((val & 0xfc) + 4) * 4;
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pl110_resize(s, n, s->rows);
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break;
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case 1: /* LCDTiming1 */
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s->timing[1] = val;
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n = (val & 0x3ff) + 1;
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pl110_resize(s, s->cols, n);
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break;
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case 2: /* LCDTiming2 */
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s->timing[2] = val;
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break;
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case 3: /* LCDTiming3 */
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s->timing[3] = val;
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break;
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case 4: /* LCDUPBASE */
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s->upbase = val;
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break;
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case 5: /* LCDLPBASE */
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s->lpbase = val;
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break;
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case 6: /* LCDIMSC */
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if (s->version != PL110) {
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goto control;
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}
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imsc:
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s->int_mask = val;
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pl110_update(s);
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break;
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case 7: /* LCDControl */
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if (s->version != PL110) {
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goto imsc;
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}
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control:
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s->cr = val;
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s->bpp = (val >> 1) & 7;
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if (pl110_enabled(s)) {
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qemu_console_resize(s->ds, s->cols, s->rows);
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}
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break;
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case 10: /* LCDICR */
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s->int_status &= ~val;
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pl110_update(s);
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break;
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default:
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hw_error("pl110_write: Bad offset %x\n", (int)offset);
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}
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}
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static CPUReadMemoryFunc * const pl110_readfn[] = {
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pl110_read,
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pl110_read,
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pl110_read
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};
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static CPUWriteMemoryFunc * const pl110_writefn[] = {
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pl110_write,
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pl110_write,
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pl110_write
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};
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static int pl110_init(SysBusDevice *dev)
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{
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pl110_state *s = FROM_SYSBUS(pl110_state, dev);
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int iomemtype;
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iomemtype = cpu_register_io_memory(pl110_readfn,
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pl110_writefn, s,
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DEVICE_NATIVE_ENDIAN);
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sysbus_init_mmio(dev, 0x1000, iomemtype);
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sysbus_init_irq(dev, &s->irq);
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s->ds = graphic_console_init(pl110_update_display,
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pl110_invalidate_display,
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NULL, NULL, s);
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return 0;
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}
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static int pl110_versatile_init(SysBusDevice *dev)
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{
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pl110_state *s = FROM_SYSBUS(pl110_state, dev);
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s->version = PL110_VERSATILE;
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return pl110_init(dev);
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}
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static int pl111_init(SysBusDevice *dev)
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{
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pl110_state *s = FROM_SYSBUS(pl110_state, dev);
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s->version = PL111;
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return pl110_init(dev);
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}
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static SysBusDeviceInfo pl110_info = {
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.init = pl110_init,
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.qdev.name = "pl110",
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.qdev.size = sizeof(pl110_state),
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.qdev.vmsd = &vmstate_pl110,
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.qdev.no_user = 1,
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};
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static SysBusDeviceInfo pl110_versatile_info = {
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.init = pl110_versatile_init,
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.qdev.name = "pl110_versatile",
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.qdev.size = sizeof(pl110_state),
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.qdev.vmsd = &vmstate_pl110,
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.qdev.no_user = 1,
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};
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static SysBusDeviceInfo pl111_info = {
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.init = pl111_init,
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.qdev.name = "pl111",
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.qdev.size = sizeof(pl110_state),
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.qdev.vmsd = &vmstate_pl110,
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.qdev.no_user = 1,
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};
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static void pl110_register_devices(void)
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{
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sysbus_register_withprop(&pl110_info);
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sysbus_register_withprop(&pl110_versatile_info);
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sysbus_register_withprop(&pl111_info);
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}
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device_init(pl110_register_devices)
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