Implement the forms of the MVE VLDR and VSTR insns which perform non-widening loads of bytes, halfwords or words from memory into vector elements of the same width (encodings T5, T6, T7). (At the moment we know for MVE and M-profile in general that vfp_access_check() can never return false, but we include the conventional return-true-on-failure check for consistency with non-M-profile translation code.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-2-peter.maydell@linaro.org
173 lines
6.6 KiB
C
173 lines
6.6 KiB
C
/*
|
|
* M-profile MVE Operations
|
|
*
|
|
* Copyright (c) 2021 Linaro, Ltd.
|
|
*
|
|
* This library is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU Lesser General Public
|
|
* License as published by the Free Software Foundation; either
|
|
* version 2.1 of the License, or (at your option) any later version.
|
|
*
|
|
* This library is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|
* Lesser General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU Lesser General Public
|
|
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
|
*/
|
|
|
|
#include "qemu/osdep.h"
|
|
#include "cpu.h"
|
|
#include "internals.h"
|
|
#include "vec_internal.h"
|
|
#include "exec/helper-proto.h"
|
|
#include "exec/cpu_ldst.h"
|
|
#include "exec/exec-all.h"
|
|
|
|
static uint16_t mve_element_mask(CPUARMState *env)
|
|
{
|
|
/*
|
|
* Return the mask of which elements in the MVE vector should be
|
|
* updated. This is a combination of multiple things:
|
|
* (1) by default, we update every lane in the vector
|
|
* (2) VPT predication stores its state in the VPR register;
|
|
* (3) low-overhead-branch tail predication will mask out part
|
|
* the vector on the final iteration of the loop
|
|
* (4) if EPSR.ECI is set then we must execute only some beats
|
|
* of the insn
|
|
* We combine all these into a 16-bit result with the same semantics
|
|
* as VPR.P0: 0 to mask the lane, 1 if it is active.
|
|
* 8-bit vector ops will look at all bits of the result;
|
|
* 16-bit ops will look at bits 0, 2, 4, ...;
|
|
* 32-bit ops will look at bits 0, 4, 8 and 12.
|
|
* Compare pseudocode GetCurInstrBeat(), though that only returns
|
|
* the 4-bit slice of the mask corresponding to a single beat.
|
|
*/
|
|
uint16_t mask = FIELD_EX32(env->v7m.vpr, V7M_VPR, P0);
|
|
|
|
if (!(env->v7m.vpr & R_V7M_VPR_MASK01_MASK)) {
|
|
mask |= 0xff;
|
|
}
|
|
if (!(env->v7m.vpr & R_V7M_VPR_MASK23_MASK)) {
|
|
mask |= 0xff00;
|
|
}
|
|
|
|
if (env->v7m.ltpsize < 4 &&
|
|
env->regs[14] <= (1 << (4 - env->v7m.ltpsize))) {
|
|
/*
|
|
* Tail predication active, and this is the last loop iteration.
|
|
* The element size is (1 << ltpsize), and we only want to process
|
|
* loopcount elements, so we want to retain the least significant
|
|
* (loopcount * esize) predicate bits and zero out bits above that.
|
|
*/
|
|
int masklen = env->regs[14] << env->v7m.ltpsize;
|
|
assert(masklen <= 16);
|
|
mask &= MAKE_64BIT_MASK(0, masklen);
|
|
}
|
|
|
|
if ((env->condexec_bits & 0xf) == 0) {
|
|
/*
|
|
* ECI bits indicate which beats are already executed;
|
|
* we handle this by effectively predicating them out.
|
|
*/
|
|
int eci = env->condexec_bits >> 4;
|
|
switch (eci) {
|
|
case ECI_NONE:
|
|
break;
|
|
case ECI_A0:
|
|
mask &= 0xfff0;
|
|
break;
|
|
case ECI_A0A1:
|
|
mask &= 0xff00;
|
|
break;
|
|
case ECI_A0A1A2:
|
|
case ECI_A0A1A2B0:
|
|
mask &= 0xf000;
|
|
break;
|
|
default:
|
|
g_assert_not_reached();
|
|
}
|
|
}
|
|
|
|
return mask;
|
|
}
|
|
|
|
static void mve_advance_vpt(CPUARMState *env)
|
|
{
|
|
/* Advance the VPT and ECI state if necessary */
|
|
uint32_t vpr = env->v7m.vpr;
|
|
unsigned mask01, mask23;
|
|
|
|
if ((env->condexec_bits & 0xf) == 0) {
|
|
env->condexec_bits = (env->condexec_bits == (ECI_A0A1A2B0 << 4)) ?
|
|
(ECI_A0 << 4) : (ECI_NONE << 4);
|
|
}
|
|
|
|
if (!(vpr & (R_V7M_VPR_MASK01_MASK | R_V7M_VPR_MASK23_MASK))) {
|
|
/* VPT not enabled, nothing to do */
|
|
return;
|
|
}
|
|
|
|
mask01 = FIELD_EX32(vpr, V7M_VPR, MASK01);
|
|
mask23 = FIELD_EX32(vpr, V7M_VPR, MASK23);
|
|
if (mask01 > 8) {
|
|
/* high bit set, but not 0b1000: invert the relevant half of P0 */
|
|
vpr ^= 0xff;
|
|
}
|
|
if (mask23 > 8) {
|
|
/* high bit set, but not 0b1000: invert the relevant half of P0 */
|
|
vpr ^= 0xff00;
|
|
}
|
|
vpr = FIELD_DP32(vpr, V7M_VPR, MASK01, mask01 << 1);
|
|
vpr = FIELD_DP32(vpr, V7M_VPR, MASK23, mask23 << 1);
|
|
env->v7m.vpr = vpr;
|
|
}
|
|
|
|
|
|
#define DO_VLDR(OP, MSIZE, LDTYPE, ESIZE, TYPE) \
|
|
void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr) \
|
|
{ \
|
|
TYPE *d = vd; \
|
|
uint16_t mask = mve_element_mask(env); \
|
|
unsigned b, e; \
|
|
/* \
|
|
* R_SXTM allows the dest reg to become UNKNOWN for abandoned \
|
|
* beats so we don't care if we update part of the dest and \
|
|
* then take an exception. \
|
|
*/ \
|
|
for (b = 0, e = 0; b < 16; b += ESIZE, e++) { \
|
|
if (mask & (1 << b)) { \
|
|
d[H##ESIZE(e)] = cpu_##LDTYPE##_data_ra(env, addr, GETPC()); \
|
|
} \
|
|
addr += MSIZE; \
|
|
} \
|
|
mve_advance_vpt(env); \
|
|
}
|
|
|
|
#define DO_VSTR(OP, MSIZE, STTYPE, ESIZE, TYPE) \
|
|
void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr) \
|
|
{ \
|
|
TYPE *d = vd; \
|
|
uint16_t mask = mve_element_mask(env); \
|
|
unsigned b, e; \
|
|
for (b = 0, e = 0; b < 16; b += ESIZE, e++) { \
|
|
if (mask & (1 << b)) { \
|
|
cpu_##STTYPE##_data_ra(env, addr, d[H##ESIZE(e)], GETPC()); \
|
|
} \
|
|
addr += MSIZE; \
|
|
} \
|
|
mve_advance_vpt(env); \
|
|
}
|
|
|
|
DO_VLDR(vldrb, 1, ldub, 1, uint8_t)
|
|
DO_VLDR(vldrh, 2, lduw, 2, uint16_t)
|
|
DO_VLDR(vldrw, 4, ldl, 4, uint32_t)
|
|
|
|
DO_VSTR(vstrb, 1, stb, 1, uint8_t)
|
|
DO_VSTR(vstrh, 2, stw, 2, uint16_t)
|
|
DO_VSTR(vstrw, 4, stl, 4, uint32_t)
|
|
|
|
#undef DO_VLDR
|
|
#undef DO_VSTR
|