50f57e09fd
There is no "version 2" of the "Lesser" General Public License. It is either "GPL version 2.0" or "Lesser GPL version 2.1". This patch replaces all occurrences of "Lesser GPL version 2" with "Lesser GPL version 2.1" in comment section. Signed-off-by: Chetan Pant <chetan4windows@gmail.com> Message-Id: <20201023122913.19561-1-chetan4windows@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
53 lines
2 KiB
Plaintext
53 lines
2 KiB
Plaintext
# AArch32 Neon load/store instruction descriptions
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#
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# Copyright (c) 2020 Linaro, Ltd
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#
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# This library is free software; you can redistribute it and/or
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# modify it under the terms of the GNU Lesser General Public
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# License as published by the Free Software Foundation; either
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# version 2.1 of the License, or (at your option) any later version.
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#
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# This library is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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# Lesser General Public License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public
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# License along with this library; if not, see <http://www.gnu.org/licenses/>.
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#
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# This file is processed by scripts/decodetree.py
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#
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# Encodings for Neon load/store instructions where the T32 encoding
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# is a simple transformation of the A32 encoding.
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# More specifically, this file covers instructions where the A32 encoding is
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# 0b1111_0100_xxx0_xxxx_xxxx_xxxx_xxxx_xxxx
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# and the T32 encoding is
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# 0b1111_1001_xxx0_xxxx_xxxx_xxxx_xxxx_xxxx
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# This file works on the A32 encoding only; calling code for T32 has to
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# transform the insn into the A32 version first.
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%vd_dp 22:1 12:4
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# Neon load/store multiple structures
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VLDST_multiple 1111 0100 0 . l:1 0 rn:4 .... itype:4 size:2 align:2 rm:4 \
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vd=%vd_dp
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# Neon load single element to all lanes
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VLD_all_lanes 1111 0100 1 . 1 0 rn:4 .... 11 n:2 size:2 t:1 a:1 rm:4 \
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vd=%vd_dp
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# Neon load/store single structure to one lane
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%imm1_5_p1 5:1 !function=plus1
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%imm1_6_p1 6:1 !function=plus1
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VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 00 n:2 reg_idx:3 align:1 rm:4 \
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vd=%vd_dp size=0 stride=1
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VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 01 n:2 reg_idx:2 align:2 rm:4 \
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vd=%vd_dp size=1 stride=%imm1_5_p1
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VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 10 n:2 reg_idx:1 align:3 rm:4 \
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vd=%vd_dp size=2 stride=%imm1_6_p1
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