Many of these should be cleaned up with proper qdev-/QOM-ification. Right now there are many catch-all headers in include/hw/ARCH depending on cpu.h, and this makes it necessary to compile these files per-target. However, fixing this does not belong in these patches. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
619 lines
15 KiB
C
619 lines
15 KiB
C
/*
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* CBUS three-pin bus and the Retu / Betty / Tahvo / Vilma / Avilma /
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* Hinku / Vinku / Ahne / Pihi chips used in various Nokia platforms.
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* Based on reverse-engineering of a linux driver.
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*
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* Copyright (C) 2008 Nokia Corporation
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* Written by Andrzej Zaborowski <andrew@openedhand.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu-common.h"
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#include "hw/irq.h"
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#include "hw/arm/devices.h"
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#include "sysemu/sysemu.h"
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//#define DEBUG
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typedef struct {
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void *opaque;
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void (*io)(void *opaque, int rw, int reg, uint16_t *val);
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int addr;
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} CBusSlave;
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typedef struct {
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CBus cbus;
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int sel;
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int dat;
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int clk;
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int bit;
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int dir;
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uint16_t val;
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qemu_irq dat_out;
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int addr;
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int reg;
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int rw;
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enum {
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cbus_address,
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cbus_value,
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} cycle;
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CBusSlave *slave[8];
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} CBusPriv;
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static void cbus_io(CBusPriv *s)
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{
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if (s->slave[s->addr])
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s->slave[s->addr]->io(s->slave[s->addr]->opaque,
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s->rw, s->reg, &s->val);
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else
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hw_error("%s: bad slave address %i\n", __FUNCTION__, s->addr);
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}
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static void cbus_cycle(CBusPriv *s)
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{
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switch (s->cycle) {
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case cbus_address:
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s->addr = (s->val >> 6) & 7;
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s->rw = (s->val >> 5) & 1;
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s->reg = (s->val >> 0) & 0x1f;
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s->cycle = cbus_value;
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s->bit = 15;
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s->dir = !s->rw;
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s->val = 0;
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if (s->rw)
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cbus_io(s);
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break;
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case cbus_value:
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if (!s->rw)
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cbus_io(s);
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s->cycle = cbus_address;
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s->bit = 8;
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s->dir = 1;
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s->val = 0;
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break;
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}
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}
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static void cbus_clk(void *opaque, int line, int level)
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{
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CBusPriv *s = (CBusPriv *) opaque;
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if (!s->sel && level && !s->clk) {
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if (s->dir)
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s->val |= s->dat << (s->bit --);
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else
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qemu_set_irq(s->dat_out, (s->val >> (s->bit --)) & 1);
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if (s->bit < 0)
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cbus_cycle(s);
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}
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s->clk = level;
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}
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static void cbus_dat(void *opaque, int line, int level)
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{
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CBusPriv *s = (CBusPriv *) opaque;
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s->dat = level;
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}
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static void cbus_sel(void *opaque, int line, int level)
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{
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CBusPriv *s = (CBusPriv *) opaque;
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if (!level) {
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s->dir = 1;
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s->bit = 8;
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s->val = 0;
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}
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s->sel = level;
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}
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CBus *cbus_init(qemu_irq dat)
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{
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CBusPriv *s = (CBusPriv *) g_malloc0(sizeof(*s));
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s->dat_out = dat;
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s->cbus.clk = qemu_allocate_irqs(cbus_clk, s, 1)[0];
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s->cbus.dat = qemu_allocate_irqs(cbus_dat, s, 1)[0];
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s->cbus.sel = qemu_allocate_irqs(cbus_sel, s, 1)[0];
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s->sel = 1;
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s->clk = 0;
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s->dat = 0;
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return &s->cbus;
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}
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void cbus_attach(CBus *bus, void *slave_opaque)
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{
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CBusSlave *slave = (CBusSlave *) slave_opaque;
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CBusPriv *s = (CBusPriv *) bus;
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s->slave[slave->addr] = slave;
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}
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/* Retu/Vilma */
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typedef struct {
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uint16_t irqst;
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uint16_t irqen;
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uint16_t cc[2];
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int channel;
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uint16_t result[16];
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uint16_t sample;
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uint16_t status;
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struct {
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uint16_t cal;
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} rtc;
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int is_vilma;
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qemu_irq irq;
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CBusSlave cbus;
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} CBusRetu;
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static void retu_interrupt_update(CBusRetu *s)
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{
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qemu_set_irq(s->irq, s->irqst & ~s->irqen);
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}
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#define RETU_REG_ASICR 0x00 /* (RO) ASIC ID & revision */
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#define RETU_REG_IDR 0x01 /* (T) Interrupt ID */
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#define RETU_REG_IMR 0x02 /* (RW) Interrupt mask */
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#define RETU_REG_RTCDSR 0x03 /* (RW) RTC seconds register */
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#define RETU_REG_RTCHMR 0x04 /* (RO) RTC hours and minutes reg */
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#define RETU_REG_RTCHMAR 0x05 /* (RW) RTC hours and minutes set reg */
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#define RETU_REG_RTCCALR 0x06 /* (RW) RTC calibration register */
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#define RETU_REG_ADCR 0x08 /* (RW) ADC result register */
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#define RETU_REG_ADCSCR 0x09 /* (RW) ADC sample control register */
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#define RETU_REG_AFCR 0x0a /* (RW) AFC register */
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#define RETU_REG_ANTIFR 0x0b /* (RW) AntiF register */
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#define RETU_REG_CALIBR 0x0c /* (RW) CalibR register*/
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#define RETU_REG_CCR1 0x0d /* (RW) Common control register 1 */
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#define RETU_REG_CCR2 0x0e /* (RW) Common control register 2 */
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#define RETU_REG_RCTRL_CLR 0x0f /* (T) Regulator clear register */
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#define RETU_REG_RCTRL_SET 0x10 /* (T) Regulator set register */
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#define RETU_REG_TXCR 0x11 /* (RW) TxC register */
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#define RETU_REG_STATUS 0x16 /* (RO) Status register */
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#define RETU_REG_WATCHDOG 0x17 /* (RW) Watchdog register */
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#define RETU_REG_AUDTXR 0x18 /* (RW) Audio Codec Tx register */
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#define RETU_REG_AUDPAR 0x19 /* (RW) AudioPA register */
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#define RETU_REG_AUDRXR1 0x1a /* (RW) Audio receive register 1 */
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#define RETU_REG_AUDRXR2 0x1b /* (RW) Audio receive register 2 */
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#define RETU_REG_SGR1 0x1c /* (RW) */
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#define RETU_REG_SCR1 0x1d /* (RW) */
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#define RETU_REG_SGR2 0x1e /* (RW) */
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#define RETU_REG_SCR2 0x1f /* (RW) */
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/* Retu Interrupt sources */
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enum {
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retu_int_pwr = 0, /* Power button */
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retu_int_char = 1, /* Charger */
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retu_int_rtcs = 2, /* Seconds */
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retu_int_rtcm = 3, /* Minutes */
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retu_int_rtcd = 4, /* Days */
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retu_int_rtca = 5, /* Alarm */
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retu_int_hook = 6, /* Hook */
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retu_int_head = 7, /* Headset */
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retu_int_adcs = 8, /* ADC sample */
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};
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/* Retu ADC channel wiring */
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enum {
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retu_adc_bsi = 1, /* BSI */
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retu_adc_batt_temp = 2, /* Battery temperature */
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retu_adc_chg_volt = 3, /* Charger voltage */
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retu_adc_head_det = 4, /* Headset detection */
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retu_adc_hook_det = 5, /* Hook detection */
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retu_adc_rf_gp = 6, /* RF GP */
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retu_adc_tx_det = 7, /* Wideband Tx detection */
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retu_adc_batt_volt = 8, /* Battery voltage */
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retu_adc_sens = 10, /* Light sensor */
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retu_adc_sens_temp = 11, /* Light sensor temperature */
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retu_adc_bbatt_volt = 12, /* Backup battery voltage */
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retu_adc_self_temp = 13, /* RETU temperature */
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};
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static inline uint16_t retu_read(CBusRetu *s, int reg)
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{
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#ifdef DEBUG
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printf("RETU read at %02x\n", reg);
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#endif
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switch (reg) {
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case RETU_REG_ASICR:
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return 0x0215 | (s->is_vilma << 7);
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case RETU_REG_IDR: /* TODO: Or is this ffs(s->irqst)? */
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return s->irqst;
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case RETU_REG_IMR:
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return s->irqen;
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case RETU_REG_RTCDSR:
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case RETU_REG_RTCHMR:
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case RETU_REG_RTCHMAR:
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/* TODO */
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return 0x0000;
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case RETU_REG_RTCCALR:
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return s->rtc.cal;
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case RETU_REG_ADCR:
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return (s->channel << 10) | s->result[s->channel];
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case RETU_REG_ADCSCR:
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return s->sample;
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case RETU_REG_AFCR:
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case RETU_REG_ANTIFR:
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case RETU_REG_CALIBR:
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/* TODO */
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return 0x0000;
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case RETU_REG_CCR1:
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return s->cc[0];
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case RETU_REG_CCR2:
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return s->cc[1];
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case RETU_REG_RCTRL_CLR:
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case RETU_REG_RCTRL_SET:
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case RETU_REG_TXCR:
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/* TODO */
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return 0x0000;
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case RETU_REG_STATUS:
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return s->status;
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case RETU_REG_WATCHDOG:
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case RETU_REG_AUDTXR:
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case RETU_REG_AUDPAR:
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case RETU_REG_AUDRXR1:
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case RETU_REG_AUDRXR2:
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case RETU_REG_SGR1:
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case RETU_REG_SCR1:
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case RETU_REG_SGR2:
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case RETU_REG_SCR2:
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/* TODO */
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return 0x0000;
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default:
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hw_error("%s: bad register %02x\n", __FUNCTION__, reg);
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}
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}
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static inline void retu_write(CBusRetu *s, int reg, uint16_t val)
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{
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#ifdef DEBUG
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printf("RETU write of %04x at %02x\n", val, reg);
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#endif
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switch (reg) {
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case RETU_REG_IDR:
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s->irqst ^= val;
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retu_interrupt_update(s);
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break;
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case RETU_REG_IMR:
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s->irqen = val;
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retu_interrupt_update(s);
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break;
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case RETU_REG_RTCDSR:
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case RETU_REG_RTCHMAR:
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/* TODO */
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break;
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case RETU_REG_RTCCALR:
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s->rtc.cal = val;
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break;
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case RETU_REG_ADCR:
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s->channel = (val >> 10) & 0xf;
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s->irqst |= 1 << retu_int_adcs;
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retu_interrupt_update(s);
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break;
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case RETU_REG_ADCSCR:
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s->sample &= ~val;
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break;
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case RETU_REG_AFCR:
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case RETU_REG_ANTIFR:
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case RETU_REG_CALIBR:
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case RETU_REG_CCR1:
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s->cc[0] = val;
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break;
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case RETU_REG_CCR2:
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s->cc[1] = val;
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break;
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case RETU_REG_RCTRL_CLR:
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case RETU_REG_RCTRL_SET:
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/* TODO */
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break;
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case RETU_REG_WATCHDOG:
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if (val == 0 && (s->cc[0] & 2))
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qemu_system_shutdown_request();
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break;
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case RETU_REG_TXCR:
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case RETU_REG_AUDTXR:
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case RETU_REG_AUDPAR:
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case RETU_REG_AUDRXR1:
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case RETU_REG_AUDRXR2:
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case RETU_REG_SGR1:
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case RETU_REG_SCR1:
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case RETU_REG_SGR2:
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case RETU_REG_SCR2:
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/* TODO */
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break;
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default:
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hw_error("%s: bad register %02x\n", __FUNCTION__, reg);
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}
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}
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static void retu_io(void *opaque, int rw, int reg, uint16_t *val)
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{
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CBusRetu *s = (CBusRetu *) opaque;
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if (rw)
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*val = retu_read(s, reg);
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else
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retu_write(s, reg, *val);
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}
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void *retu_init(qemu_irq irq, int vilma)
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{
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CBusRetu *s = (CBusRetu *) g_malloc0(sizeof(*s));
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s->irq = irq;
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s->irqen = 0xffff;
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s->irqst = 0x0000;
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s->status = 0x0020;
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s->is_vilma = !!vilma;
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s->rtc.cal = 0x01;
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s->result[retu_adc_bsi] = 0x3c2;
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s->result[retu_adc_batt_temp] = 0x0fc;
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s->result[retu_adc_chg_volt] = 0x165;
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s->result[retu_adc_head_det] = 123;
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s->result[retu_adc_hook_det] = 1023;
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s->result[retu_adc_rf_gp] = 0x11;
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s->result[retu_adc_tx_det] = 0x11;
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s->result[retu_adc_batt_volt] = 0x250;
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s->result[retu_adc_sens] = 2;
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s->result[retu_adc_sens_temp] = 0x11;
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s->result[retu_adc_bbatt_volt] = 0x3d0;
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s->result[retu_adc_self_temp] = 0x330;
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s->cbus.opaque = s;
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s->cbus.io = retu_io;
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s->cbus.addr = 1;
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return &s->cbus;
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}
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void retu_key_event(void *retu, int state)
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{
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CBusSlave *slave = (CBusSlave *) retu;
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CBusRetu *s = (CBusRetu *) slave->opaque;
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s->irqst |= 1 << retu_int_pwr;
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retu_interrupt_update(s);
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if (state)
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s->status &= ~(1 << 5);
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else
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s->status |= 1 << 5;
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}
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#if 0
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static void retu_head_event(void *retu, int state)
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{
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CBusSlave *slave = (CBusSlave *) retu;
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CBusRetu *s = (CBusRetu *) slave->opaque;
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if ((s->cc[0] & 0x500) == 0x500) { /* TODO: Which bits? */
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/* TODO: reissue the interrupt every 100ms or so. */
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s->irqst |= 1 << retu_int_head;
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retu_interrupt_update(s);
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}
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if (state)
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s->result[retu_adc_head_det] = 50;
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else
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s->result[retu_adc_head_det] = 123;
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}
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static void retu_hook_event(void *retu, int state)
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{
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CBusSlave *slave = (CBusSlave *) retu;
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CBusRetu *s = (CBusRetu *) slave->opaque;
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if ((s->cc[0] & 0x500) == 0x500) {
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/* TODO: reissue the interrupt every 100ms or so. */
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s->irqst |= 1 << retu_int_hook;
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retu_interrupt_update(s);
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}
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if (state)
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s->result[retu_adc_hook_det] = 50;
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else
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s->result[retu_adc_hook_det] = 123;
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}
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#endif
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|
|
/* Tahvo/Betty */
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|
typedef struct {
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uint16_t irqst;
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uint16_t irqen;
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uint8_t charger;
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uint8_t backlight;
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uint16_t usbr;
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uint16_t power;
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int is_betty;
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qemu_irq irq;
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CBusSlave cbus;
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} CBusTahvo;
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static void tahvo_interrupt_update(CBusTahvo *s)
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{
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qemu_set_irq(s->irq, s->irqst & ~s->irqen);
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}
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|
|
#define TAHVO_REG_ASICR 0x00 /* (RO) ASIC ID & revision */
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#define TAHVO_REG_IDR 0x01 /* (T) Interrupt ID */
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#define TAHVO_REG_IDSR 0x02 /* (RO) Interrupt status */
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#define TAHVO_REG_IMR 0x03 /* (RW) Interrupt mask */
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#define TAHVO_REG_CHAPWMR 0x04 /* (RW) Charger PWM */
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#define TAHVO_REG_LEDPWMR 0x05 /* (RW) LED PWM */
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#define TAHVO_REG_USBR 0x06 /* (RW) USB control */
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#define TAHVO_REG_RCR 0x07 /* (RW) Some kind of power management */
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|
#define TAHVO_REG_CCR1 0x08 /* (RW) Common control register 1 */
|
|
#define TAHVO_REG_CCR2 0x09 /* (RW) Common control register 2 */
|
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#define TAHVO_REG_TESTR1 0x0a /* (RW) Test register 1 */
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#define TAHVO_REG_TESTR2 0x0b /* (RW) Test register 2 */
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#define TAHVO_REG_NOPR 0x0c /* (RW) Number of periods */
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#define TAHVO_REG_FRR 0x0d /* (RO) FR */
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static inline uint16_t tahvo_read(CBusTahvo *s, int reg)
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{
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#ifdef DEBUG
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printf("TAHVO read at %02x\n", reg);
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#endif
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switch (reg) {
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case TAHVO_REG_ASICR:
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return 0x0021 | (s->is_betty ? 0x0b00 : 0x0300); /* 22 in N810 */
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case TAHVO_REG_IDR:
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case TAHVO_REG_IDSR: /* XXX: what does this do? */
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return s->irqst;
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case TAHVO_REG_IMR:
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return s->irqen;
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case TAHVO_REG_CHAPWMR:
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return s->charger;
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case TAHVO_REG_LEDPWMR:
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return s->backlight;
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case TAHVO_REG_USBR:
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return s->usbr;
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case TAHVO_REG_RCR:
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return s->power;
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case TAHVO_REG_CCR1:
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case TAHVO_REG_CCR2:
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case TAHVO_REG_TESTR1:
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case TAHVO_REG_TESTR2:
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case TAHVO_REG_NOPR:
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case TAHVO_REG_FRR:
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return 0x0000;
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default:
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hw_error("%s: bad register %02x\n", __FUNCTION__, reg);
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}
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}
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static inline void tahvo_write(CBusTahvo *s, int reg, uint16_t val)
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{
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#ifdef DEBUG
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printf("TAHVO write of %04x at %02x\n", val, reg);
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#endif
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switch (reg) {
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case TAHVO_REG_IDR:
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s->irqst ^= val;
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tahvo_interrupt_update(s);
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break;
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case TAHVO_REG_IMR:
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s->irqen = val;
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tahvo_interrupt_update(s);
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break;
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case TAHVO_REG_CHAPWMR:
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s->charger = val;
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break;
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case TAHVO_REG_LEDPWMR:
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if (s->backlight != (val & 0x7f)) {
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s->backlight = val & 0x7f;
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printf("%s: LCD backlight now at %i / 127\n",
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__FUNCTION__, s->backlight);
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}
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break;
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case TAHVO_REG_USBR:
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s->usbr = val;
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break;
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case TAHVO_REG_RCR:
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s->power = val;
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break;
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case TAHVO_REG_CCR1:
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case TAHVO_REG_CCR2:
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case TAHVO_REG_TESTR1:
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case TAHVO_REG_TESTR2:
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case TAHVO_REG_NOPR:
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case TAHVO_REG_FRR:
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break;
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default:
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hw_error("%s: bad register %02x\n", __FUNCTION__, reg);
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}
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}
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static void tahvo_io(void *opaque, int rw, int reg, uint16_t *val)
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{
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CBusTahvo *s = (CBusTahvo *) opaque;
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if (rw)
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*val = tahvo_read(s, reg);
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else
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tahvo_write(s, reg, *val);
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}
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void *tahvo_init(qemu_irq irq, int betty)
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{
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CBusTahvo *s = (CBusTahvo *) g_malloc0(sizeof(*s));
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s->irq = irq;
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s->irqen = 0xffff;
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s->irqst = 0x0000;
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s->is_betty = !!betty;
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s->cbus.opaque = s;
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s->cbus.io = tahvo_io;
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s->cbus.addr = 2;
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return &s->cbus;
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}
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