Allows edk2 detect virtio-mmio devices and pcie ecam. See comment in hw/i386/microvm-dt.c for more details. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Sergio Lopez <slp@redhat.com> Message-Id: <20211014193617.2475578-1-kraxel@redhat.com>
342 lines
11 KiB
C
342 lines
11 KiB
C
/*
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* microvm device tree support
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*
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* This generates an device tree for microvm and exports it via fw_cfg
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* as "etc/fdt" to the firmware (edk2 specifically).
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*
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* The use case is to allow edk2 find the pcie ecam and the virtio
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* devices, without adding an ACPI parser, reusing the fdt parser
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* which is needed anyway for the arm platform.
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*
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* Note 1: The device tree is incomplete. CPUs and memory is missing
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* for example, those can be detected using other fw_cfg files.
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* Also pci ecam irq routing is not there, edk2 doesn't use
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* interrupts.
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*
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* Note 2: This is for firmware only. OSes should use the more
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* complete ACPI tables for hardware discovery.
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*
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* ----------------------------------------------------------------------
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/cutils.h"
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#include "sysemu/device_tree.h"
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#include "hw/char/serial.h"
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#include "hw/i386/fw_cfg.h"
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#include "hw/rtc/mc146818rtc.h"
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#include "hw/sysbus.h"
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#include "hw/virtio/virtio-mmio.h"
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#include "hw/usb/xhci.h"
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#include "microvm-dt.h"
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static bool debug;
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static void dt_add_microvm_irq(MicrovmMachineState *mms,
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const char *nodename, uint32_t irq)
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{
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int index = 0;
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if (irq >= IO_APIC_SECONDARY_IRQBASE) {
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irq -= IO_APIC_SECONDARY_IRQBASE;
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index++;
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}
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qemu_fdt_setprop_cell(mms->fdt, nodename, "interrupt-parent",
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mms->ioapic_phandle[index]);
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qemu_fdt_setprop_cells(mms->fdt, nodename, "interrupts", irq, 0);
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}
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static void dt_add_virtio(MicrovmMachineState *mms, VirtIOMMIOProxy *mmio)
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{
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SysBusDevice *dev = SYS_BUS_DEVICE(mmio);
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VirtioBusState *mmio_virtio_bus = &mmio->bus;
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BusState *mmio_bus = &mmio_virtio_bus->parent_obj;
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char *nodename;
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if (QTAILQ_EMPTY(&mmio_bus->children)) {
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return;
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}
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hwaddr base = dev->mmio[0].addr;
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hwaddr size = 512;
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unsigned index = (base - VIRTIO_MMIO_BASE) / size;
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uint32_t irq = mms->virtio_irq_base + index;
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nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
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qemu_fdt_add_subnode(mms->fdt, nodename);
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qemu_fdt_setprop_string(mms->fdt, nodename, "compatible", "virtio,mmio");
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qemu_fdt_setprop_sized_cells(mms->fdt, nodename, "reg", 2, base, 2, size);
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qemu_fdt_setprop(mms->fdt, nodename, "dma-coherent", NULL, 0);
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dt_add_microvm_irq(mms, nodename, irq);
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g_free(nodename);
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}
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static void dt_add_xhci(MicrovmMachineState *mms)
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{
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const char compat[] = "generic-xhci";
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uint32_t irq = MICROVM_XHCI_IRQ;
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hwaddr base = MICROVM_XHCI_BASE;
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hwaddr size = XHCI_LEN_REGS;
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char *nodename;
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nodename = g_strdup_printf("/usb@%" PRIx64, base);
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qemu_fdt_add_subnode(mms->fdt, nodename);
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qemu_fdt_setprop(mms->fdt, nodename, "compatible", compat, sizeof(compat));
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qemu_fdt_setprop_sized_cells(mms->fdt, nodename, "reg", 2, base, 2, size);
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qemu_fdt_setprop(mms->fdt, nodename, "dma-coherent", NULL, 0);
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dt_add_microvm_irq(mms, nodename, irq);
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g_free(nodename);
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}
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static void dt_add_pcie(MicrovmMachineState *mms)
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{
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hwaddr base = PCIE_MMIO_BASE;
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int nr_pcie_buses;
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char *nodename;
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nodename = g_strdup_printf("/pcie@%" PRIx64, base);
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qemu_fdt_add_subnode(mms->fdt, nodename);
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qemu_fdt_setprop_string(mms->fdt, nodename,
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"compatible", "pci-host-ecam-generic");
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qemu_fdt_setprop_string(mms->fdt, nodename, "device_type", "pci");
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qemu_fdt_setprop_cell(mms->fdt, nodename, "#address-cells", 3);
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qemu_fdt_setprop_cell(mms->fdt, nodename, "#size-cells", 2);
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qemu_fdt_setprop_cell(mms->fdt, nodename, "linux,pci-domain", 0);
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qemu_fdt_setprop(mms->fdt, nodename, "dma-coherent", NULL, 0);
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qemu_fdt_setprop_sized_cells(mms->fdt, nodename, "reg",
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2, PCIE_ECAM_BASE, 2, PCIE_ECAM_SIZE);
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if (mms->gpex.mmio64.size) {
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qemu_fdt_setprop_sized_cells(mms->fdt, nodename, "ranges",
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1, FDT_PCI_RANGE_MMIO,
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2, mms->gpex.mmio32.base,
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2, mms->gpex.mmio32.base,
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2, mms->gpex.mmio32.size,
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1, FDT_PCI_RANGE_MMIO_64BIT,
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2, mms->gpex.mmio64.base,
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2, mms->gpex.mmio64.base,
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2, mms->gpex.mmio64.size);
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} else {
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qemu_fdt_setprop_sized_cells(mms->fdt, nodename, "ranges",
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1, FDT_PCI_RANGE_MMIO,
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2, mms->gpex.mmio32.base,
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2, mms->gpex.mmio32.base,
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2, mms->gpex.mmio32.size);
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}
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nr_pcie_buses = PCIE_ECAM_SIZE / PCIE_MMCFG_SIZE_MIN;
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qemu_fdt_setprop_cells(mms->fdt, nodename, "bus-range", 0,
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nr_pcie_buses - 1);
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}
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static void dt_add_ioapic(MicrovmMachineState *mms, SysBusDevice *dev)
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{
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hwaddr base = dev->mmio[0].addr;
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char *nodename;
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uint32_t ph;
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int index;
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switch (base) {
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case IO_APIC_DEFAULT_ADDRESS:
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index = 0;
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break;
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case IO_APIC_SECONDARY_ADDRESS:
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index = 1;
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break;
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default:
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fprintf(stderr, "unknown ioapic @ %" PRIx64 "\n", base);
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return;
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}
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nodename = g_strdup_printf("/ioapic%d@%" PRIx64, index + 1, base);
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qemu_fdt_add_subnode(mms->fdt, nodename);
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qemu_fdt_setprop_string(mms->fdt, nodename,
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"compatible", "intel,ce4100-ioapic");
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qemu_fdt_setprop(mms->fdt, nodename, "interrupt-controller", NULL, 0);
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qemu_fdt_setprop_cell(mms->fdt, nodename, "#interrupt-cells", 0x2);
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qemu_fdt_setprop_cell(mms->fdt, nodename, "#address-cells", 0x2);
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qemu_fdt_setprop_sized_cells(mms->fdt, nodename, "reg",
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2, base, 2, 0x1000);
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ph = qemu_fdt_alloc_phandle(mms->fdt);
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qemu_fdt_setprop_cell(mms->fdt, nodename, "phandle", ph);
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qemu_fdt_setprop_cell(mms->fdt, nodename, "linux,phandle", ph);
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mms->ioapic_phandle[index] = ph;
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g_free(nodename);
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}
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static void dt_add_isa_serial(MicrovmMachineState *mms, ISADevice *dev)
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{
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const char compat[] = "ns16550";
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uint32_t irq = object_property_get_int(OBJECT(dev), "irq", NULL);
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hwaddr base = object_property_get_int(OBJECT(dev), "iobase", NULL);
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hwaddr size = 8;
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char *nodename;
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nodename = g_strdup_printf("/serial@%" PRIx64, base);
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qemu_fdt_add_subnode(mms->fdt, nodename);
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qemu_fdt_setprop(mms->fdt, nodename, "compatible", compat, sizeof(compat));
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qemu_fdt_setprop_sized_cells(mms->fdt, nodename, "reg", 2, base, 2, size);
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dt_add_microvm_irq(mms, nodename, irq);
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if (base == 0x3f8 /* com1 */) {
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qemu_fdt_setprop_string(mms->fdt, "/chosen", "stdout-path", nodename);
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}
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g_free(nodename);
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}
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static void dt_add_isa_rtc(MicrovmMachineState *mms, ISADevice *dev)
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{
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const char compat[] = "motorola,mc146818";
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uint32_t irq = RTC_ISA_IRQ;
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hwaddr base = RTC_ISA_BASE;
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hwaddr size = 8;
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char *nodename;
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nodename = g_strdup_printf("/rtc@%" PRIx64, base);
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qemu_fdt_add_subnode(mms->fdt, nodename);
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qemu_fdt_setprop(mms->fdt, nodename, "compatible", compat, sizeof(compat));
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qemu_fdt_setprop_sized_cells(mms->fdt, nodename, "reg", 2, base, 2, size);
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dt_add_microvm_irq(mms, nodename, irq);
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g_free(nodename);
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}
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static void dt_setup_isa_bus(MicrovmMachineState *mms, DeviceState *bridge)
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{
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BusState *bus = qdev_get_child_bus(bridge, "isa.0");
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BusChild *kid;
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Object *obj;
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QTAILQ_FOREACH(kid, &bus->children, sibling) {
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DeviceState *dev = kid->child;
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/* serial */
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obj = object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL);
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if (obj) {
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dt_add_isa_serial(mms, ISA_DEVICE(obj));
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continue;
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}
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/* rtc */
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obj = object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC);
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if (obj) {
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dt_add_isa_rtc(mms, ISA_DEVICE(obj));
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continue;
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}
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if (debug) {
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fprintf(stderr, "%s: unhandled: %s\n", __func__,
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object_get_typename(OBJECT(dev)));
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}
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}
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}
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static void dt_setup_sys_bus(MicrovmMachineState *mms)
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{
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BusState *bus;
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BusChild *kid;
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Object *obj;
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/* sysbus devices */
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bus = sysbus_get_default();
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QTAILQ_FOREACH(kid, &bus->children, sibling) {
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DeviceState *dev = kid->child;
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/* ioapic */
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obj = object_dynamic_cast(OBJECT(dev), TYPE_IOAPIC);
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if (obj) {
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dt_add_ioapic(mms, SYS_BUS_DEVICE(obj));
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continue;
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}
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}
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QTAILQ_FOREACH(kid, &bus->children, sibling) {
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DeviceState *dev = kid->child;
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/* virtio */
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obj = object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MMIO);
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if (obj) {
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dt_add_virtio(mms, VIRTIO_MMIO(obj));
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continue;
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}
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/* xhci */
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obj = object_dynamic_cast(OBJECT(dev), TYPE_XHCI_SYSBUS);
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if (obj) {
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dt_add_xhci(mms);
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continue;
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}
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/* pcie */
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obj = object_dynamic_cast(OBJECT(dev), TYPE_GPEX_HOST);
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if (obj) {
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dt_add_pcie(mms);
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continue;
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}
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/* isa */
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obj = object_dynamic_cast(OBJECT(dev), "isabus-bridge");
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if (obj) {
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dt_setup_isa_bus(mms, DEVICE(obj));
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continue;
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}
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if (debug) {
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obj = object_dynamic_cast(OBJECT(dev), TYPE_IOAPIC);
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if (obj) {
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/* ioapic already added in first pass */
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continue;
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}
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fprintf(stderr, "%s: unhandled: %s\n", __func__,
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object_get_typename(OBJECT(dev)));
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}
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}
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}
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void dt_setup_microvm(MicrovmMachineState *mms)
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{
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X86MachineState *x86ms = X86_MACHINE(mms);
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int size = 0;
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mms->fdt = create_device_tree(&size);
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/* root node */
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qemu_fdt_setprop_string(mms->fdt, "/", "compatible", "linux,microvm");
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qemu_fdt_setprop_cell(mms->fdt, "/", "#address-cells", 0x2);
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qemu_fdt_setprop_cell(mms->fdt, "/", "#size-cells", 0x2);
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qemu_fdt_add_subnode(mms->fdt, "/chosen");
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dt_setup_sys_bus(mms);
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/* add to fw_cfg */
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fprintf(stderr, "%s: add etc/fdt to fw_cfg\n", __func__);
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fw_cfg_add_file(x86ms->fw_cfg, "etc/fdt", mms->fdt, size);
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if (debug) {
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fprintf(stderr, "%s: writing microvm.fdt\n", __func__);
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g_file_set_contents("microvm.fdt", mms->fdt, size, NULL);
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int ret = system("dtc -I dtb -O dts microvm.fdt");
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if (ret != 0) {
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fprintf(stderr, "%s: oops, dtc not installed?\n", __func__);
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}
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}
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}
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