56f6e31e7b
This is an initial support for Microchip PolarFire SoC Icicle Kit. The Icicle Kit board integrates a PolarFire SoC, with one SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA. For more details about Microchip PolarFire Soc, please see: https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga Unlike SiFive FU540, the RISC-V core resect vector is at 0x20220000. The following perepherals are created as an unimplemented device: - Bus Error Uint 0/1/2/3/4 - L2 cache controller - SYSREG - MPUCFG - IOSCBCFG More devices will be added later. The BIOS image used by this machine is hss.bin, aka Hart Software Services, which can be built from: https://github.com/polarfire-soc/hart-software-services To launch this machine: $ qemu-system-riscv64 -nographic -M microchip-icicle-kit The memory is set to 1 GiB by default to match the hardware. A sanity check on ram size is performed in the machine init routine to prompt user to increase the RAM size to > 1 GiB when less than 1 GiB ram is detected. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-5-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
22 lines
1.2 KiB
Meson
22 lines
1.2 KiB
Meson
riscv_ss = ss.source_set()
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riscv_ss.add(files('boot.c'), fdt)
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riscv_ss.add(files('numa.c'))
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riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
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riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
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riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
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riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_clint.c'))
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riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_gpio.c'))
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riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
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riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
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riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
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riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
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riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e_prci.c'))
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riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
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riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
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riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c'))
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riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
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riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
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riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
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hw_arch += {'riscv': riscv_ss}
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