Multicore L1 cache modelling is introduced and is supported for both full system emulation and linux-user. For full-system emulation, L1 icache and dcache are maintained for each available core, since this information is exposed to the plugin through `qemu_plugin_n_vcpus()`. For linux-user, a static number of cores is assumed (default 1 core, and can be provided as a plugin argument `cores=N`). Every memory access goes through one of these caches, this approach is taken as it's somewhat akin to what happens on real setup, where a program that dispatches more threads than the available cores, they'll thrash each other Signed-off-by: Mahmoud Mandour <ma.mandourr@gmail.com> Message-Id: <20210803151301.123581-2-ma.mandourr@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
729 lines
19 KiB
C
729 lines
19 KiB
C
/*
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* Copyright (C) 2021, Mahmoud Mandour <ma.mandourr@gmail.com>
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*
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* License: GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include <inttypes.h>
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#include <stdio.h>
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#include <glib.h>
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#include <qemu-plugin.h>
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QEMU_PLUGIN_EXPORT int qemu_plugin_version = QEMU_PLUGIN_VERSION;
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static enum qemu_plugin_mem_rw rw = QEMU_PLUGIN_MEM_RW;
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static GHashTable *miss_ht;
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static GMutex hashtable_lock;
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static GRand *rng;
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static int limit;
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static bool sys;
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enum EvictionPolicy {
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LRU,
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FIFO,
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RAND,
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};
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enum EvictionPolicy policy;
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/*
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* A CacheSet is a set of cache blocks. A memory block that maps to a set can be
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* put in any of the blocks inside the set. The number of block per set is
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* called the associativity (assoc).
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*
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* Each block contains the the stored tag and a valid bit. Since this is not
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* a functional simulator, the data itself is not stored. We only identify
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* whether a block is in the cache or not by searching for its tag.
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*
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* In order to search for memory data in the cache, the set identifier and tag
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* are extracted from the address and the set is probed to see whether a tag
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* match occur.
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*
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* An address is logically divided into three portions: The block offset,
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* the set number, and the tag.
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*
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* The set number is used to identify the set in which the block may exist.
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* The tag is compared against all the tags of a set to search for a match. If a
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* match is found, then the access is a hit.
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*
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* The CacheSet also contains bookkeaping information about eviction details.
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*/
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typedef struct {
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uint64_t tag;
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bool valid;
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} CacheBlock;
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typedef struct {
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CacheBlock *blocks;
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uint64_t *lru_priorities;
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uint64_t lru_gen_counter;
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GQueue *fifo_queue;
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} CacheSet;
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typedef struct {
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CacheSet *sets;
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int num_sets;
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int cachesize;
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int assoc;
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int blksize_shift;
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uint64_t set_mask;
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uint64_t tag_mask;
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uint64_t accesses;
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uint64_t misses;
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} Cache;
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typedef struct {
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char *disas_str;
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const char *symbol;
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uint64_t addr;
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uint64_t dmisses;
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uint64_t imisses;
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} InsnData;
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void (*update_hit)(Cache *cache, int set, int blk);
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void (*update_miss)(Cache *cache, int set, int blk);
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void (*metadata_init)(Cache *cache);
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void (*metadata_destroy)(Cache *cache);
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static int cores;
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static Cache **dcaches, **icaches;
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static GMutex *dcache_locks;
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static GMutex *icache_locks;
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static uint64_t all_dmem_accesses;
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static uint64_t all_imem_accesses;
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static uint64_t all_imisses;
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static uint64_t all_dmisses;
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static int pow_of_two(int num)
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{
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g_assert((num & (num - 1)) == 0);
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int ret = 0;
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while (num /= 2) {
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ret++;
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}
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return ret;
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}
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/*
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* LRU evection policy: For each set, a generation counter is maintained
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* alongside a priority array.
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*
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* On each set access, the generation counter is incremented.
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*
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* On a cache hit: The hit-block is assigned the current generation counter,
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* indicating that it is the most recently used block.
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*
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* On a cache miss: The block with the least priority is searched and replaced
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* with the newly-cached block, of which the priority is set to the current
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* generation number.
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*/
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static void lru_priorities_init(Cache *cache)
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{
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int i;
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for (i = 0; i < cache->num_sets; i++) {
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cache->sets[i].lru_priorities = g_new0(uint64_t, cache->assoc);
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cache->sets[i].lru_gen_counter = 0;
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}
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}
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static void lru_update_blk(Cache *cache, int set_idx, int blk_idx)
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{
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CacheSet *set = &cache->sets[set_idx];
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set->lru_priorities[blk_idx] = cache->sets[set_idx].lru_gen_counter;
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set->lru_gen_counter++;
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}
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static int lru_get_lru_block(Cache *cache, int set_idx)
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{
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int i, min_idx, min_priority;
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min_priority = cache->sets[set_idx].lru_priorities[0];
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min_idx = 0;
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for (i = 1; i < cache->assoc; i++) {
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if (cache->sets[set_idx].lru_priorities[i] < min_priority) {
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min_priority = cache->sets[set_idx].lru_priorities[i];
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min_idx = i;
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}
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}
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return min_idx;
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}
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static void lru_priorities_destroy(Cache *cache)
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{
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int i;
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for (i = 0; i < cache->num_sets; i++) {
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g_free(cache->sets[i].lru_priorities);
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}
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}
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/*
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* FIFO eviction policy: a FIFO queue is maintained for each CacheSet that
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* stores accesses to the cache.
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*
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* On a compulsory miss: The block index is enqueued to the fifo_queue to
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* indicate that it's the latest cached block.
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*
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* On a conflict miss: The first-in block is removed from the cache and the new
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* block is put in its place and enqueued to the FIFO queue.
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*/
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static void fifo_init(Cache *cache)
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{
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int i;
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for (i = 0; i < cache->num_sets; i++) {
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cache->sets[i].fifo_queue = g_queue_new();
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}
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}
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static int fifo_get_first_block(Cache *cache, int set)
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{
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GQueue *q = cache->sets[set].fifo_queue;
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return GPOINTER_TO_INT(g_queue_pop_tail(q));
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}
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static void fifo_update_on_miss(Cache *cache, int set, int blk_idx)
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{
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GQueue *q = cache->sets[set].fifo_queue;
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g_queue_push_head(q, GINT_TO_POINTER(blk_idx));
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}
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static void fifo_destroy(Cache *cache)
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{
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int i;
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for (i = 0; i < cache->num_sets; i++) {
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g_queue_free(cache->sets[i].fifo_queue);
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}
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}
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static inline uint64_t extract_tag(Cache *cache, uint64_t addr)
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{
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return addr & cache->tag_mask;
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}
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static inline uint64_t extract_set(Cache *cache, uint64_t addr)
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{
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return (addr & cache->set_mask) >> cache->blksize_shift;
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}
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static const char *cache_config_error(int blksize, int assoc, int cachesize)
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{
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if (cachesize % blksize != 0) {
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return "cache size must be divisible by block size";
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} else if (cachesize % (blksize * assoc) != 0) {
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return "cache size must be divisible by set size (assoc * block size)";
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} else {
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return NULL;
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}
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}
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static bool bad_cache_params(int blksize, int assoc, int cachesize)
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{
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return (cachesize % blksize) != 0 || (cachesize % (blksize * assoc) != 0);
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}
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static Cache *cache_init(int blksize, int assoc, int cachesize)
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{
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Cache *cache;
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int i;
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uint64_t blk_mask;
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/*
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* This function shall not be called directly, and hence expects suitable
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* parameters.
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*/
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g_assert(!bad_cache_params(blksize, assoc, cachesize));
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cache = g_new(Cache, 1);
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cache->assoc = assoc;
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cache->cachesize = cachesize;
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cache->num_sets = cachesize / (blksize * assoc);
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cache->sets = g_new(CacheSet, cache->num_sets);
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cache->blksize_shift = pow_of_two(blksize);
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cache->accesses = 0;
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cache->misses = 0;
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for (i = 0; i < cache->num_sets; i++) {
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cache->sets[i].blocks = g_new0(CacheBlock, assoc);
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}
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blk_mask = blksize - 1;
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cache->set_mask = ((cache->num_sets - 1) << cache->blksize_shift);
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cache->tag_mask = ~(cache->set_mask | blk_mask);
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if (metadata_init) {
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metadata_init(cache);
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}
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return cache;
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}
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static Cache **caches_init(int blksize, int assoc, int cachesize)
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{
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Cache **caches;
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int i;
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if (bad_cache_params(blksize, assoc, cachesize)) {
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return NULL;
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}
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caches = g_new(Cache *, cores);
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for (i = 0; i < cores; i++) {
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caches[i] = cache_init(blksize, assoc, cachesize);
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}
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return caches;
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}
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static int get_invalid_block(Cache *cache, uint64_t set)
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{
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int i;
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for (i = 0; i < cache->assoc; i++) {
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if (!cache->sets[set].blocks[i].valid) {
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return i;
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}
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}
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return -1;
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}
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static int get_replaced_block(Cache *cache, int set)
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{
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switch (policy) {
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case RAND:
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return g_rand_int_range(rng, 0, cache->assoc);
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case LRU:
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return lru_get_lru_block(cache, set);
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case FIFO:
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return fifo_get_first_block(cache, set);
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default:
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g_assert_not_reached();
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}
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}
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static int in_cache(Cache *cache, uint64_t addr)
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{
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int i;
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uint64_t tag, set;
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tag = extract_tag(cache, addr);
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set = extract_set(cache, addr);
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for (i = 0; i < cache->assoc; i++) {
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if (cache->sets[set].blocks[i].tag == tag &&
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cache->sets[set].blocks[i].valid) {
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return i;
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}
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}
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return -1;
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}
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/**
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* access_cache(): Simulate a cache access
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* @cache: The cache under simulation
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* @addr: The address of the requested memory location
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*
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* Returns true if the requsted data is hit in the cache and false when missed.
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* The cache is updated on miss for the next access.
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*/
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static bool access_cache(Cache *cache, uint64_t addr)
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{
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int hit_blk, replaced_blk;
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uint64_t tag, set;
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tag = extract_tag(cache, addr);
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set = extract_set(cache, addr);
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hit_blk = in_cache(cache, addr);
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if (hit_blk != -1) {
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if (update_hit) {
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update_hit(cache, set, hit_blk);
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}
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return true;
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}
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replaced_blk = get_invalid_block(cache, set);
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if (replaced_blk == -1) {
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replaced_blk = get_replaced_block(cache, set);
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}
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if (update_miss) {
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update_miss(cache, set, replaced_blk);
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}
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cache->sets[set].blocks[replaced_blk].tag = tag;
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cache->sets[set].blocks[replaced_blk].valid = true;
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return false;
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}
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static void vcpu_mem_access(unsigned int vcpu_index, qemu_plugin_meminfo_t info,
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uint64_t vaddr, void *userdata)
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{
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uint64_t effective_addr;
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struct qemu_plugin_hwaddr *hwaddr;
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int cache_idx;
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InsnData *insn;
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hwaddr = qemu_plugin_get_hwaddr(info, vaddr);
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if (hwaddr && qemu_plugin_hwaddr_is_io(hwaddr)) {
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return;
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}
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effective_addr = hwaddr ? qemu_plugin_hwaddr_phys_addr(hwaddr) : vaddr;
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cache_idx = vcpu_index % cores;
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g_mutex_lock(&dcache_locks[cache_idx]);
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if (!access_cache(dcaches[cache_idx], effective_addr)) {
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insn = (InsnData *) userdata;
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__atomic_fetch_add(&insn->dmisses, 1, __ATOMIC_SEQ_CST);
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dcaches[cache_idx]->misses++;
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}
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dcaches[cache_idx]->accesses++;
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g_mutex_unlock(&dcache_locks[cache_idx]);
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}
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static void vcpu_insn_exec(unsigned int vcpu_index, void *userdata)
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{
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uint64_t insn_addr;
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InsnData *insn;
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int cache_idx;
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insn_addr = ((InsnData *) userdata)->addr;
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cache_idx = vcpu_index % cores;
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g_mutex_lock(&icache_locks[cache_idx]);
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if (!access_cache(icaches[cache_idx], insn_addr)) {
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insn = (InsnData *) userdata;
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__atomic_fetch_add(&insn->imisses, 1, __ATOMIC_SEQ_CST);
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icaches[cache_idx]->misses++;
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}
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icaches[cache_idx]->accesses++;
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g_mutex_unlock(&icache_locks[cache_idx]);
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}
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static void vcpu_tb_trans(qemu_plugin_id_t id, struct qemu_plugin_tb *tb)
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{
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size_t n_insns;
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size_t i;
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InsnData *data;
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n_insns = qemu_plugin_tb_n_insns(tb);
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for (i = 0; i < n_insns; i++) {
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struct qemu_plugin_insn *insn = qemu_plugin_tb_get_insn(tb, i);
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uint64_t effective_addr;
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if (sys) {
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effective_addr = (uint64_t) qemu_plugin_insn_haddr(insn);
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} else {
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effective_addr = (uint64_t) qemu_plugin_insn_vaddr(insn);
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}
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/*
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* Instructions might get translated multiple times, we do not create
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* new entries for those instructions. Instead, we fetch the same
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* entry from the hash table and register it for the callback again.
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*/
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g_mutex_lock(&hashtable_lock);
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data = g_hash_table_lookup(miss_ht, GUINT_TO_POINTER(effective_addr));
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if (data == NULL) {
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data = g_new0(InsnData, 1);
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data->disas_str = qemu_plugin_insn_disas(insn);
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data->symbol = qemu_plugin_insn_symbol(insn);
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data->addr = effective_addr;
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g_hash_table_insert(miss_ht, GUINT_TO_POINTER(effective_addr),
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(gpointer) data);
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}
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g_mutex_unlock(&hashtable_lock);
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qemu_plugin_register_vcpu_mem_cb(insn, vcpu_mem_access,
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QEMU_PLUGIN_CB_NO_REGS,
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rw, data);
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qemu_plugin_register_vcpu_insn_exec_cb(insn, vcpu_insn_exec,
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QEMU_PLUGIN_CB_NO_REGS, data);
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}
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}
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static void insn_free(gpointer data)
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{
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InsnData *insn = (InsnData *) data;
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g_free(insn->disas_str);
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g_free(insn);
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}
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static void cache_free(Cache *cache)
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{
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for (int i = 0; i < cache->num_sets; i++) {
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g_free(cache->sets[i].blocks);
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}
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if (metadata_destroy) {
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metadata_destroy(cache);
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}
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g_free(cache->sets);
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g_free(cache);
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}
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static void caches_free(Cache **caches)
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{
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int i;
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for (i = 0; i < cores; i++) {
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cache_free(caches[i]);
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}
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}
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static int dcmp(gconstpointer a, gconstpointer b)
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{
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InsnData *insn_a = (InsnData *) a;
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InsnData *insn_b = (InsnData *) b;
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return insn_a->dmisses < insn_b->dmisses ? 1 : -1;
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}
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static void append_stats_line(GString *line, uint64_t daccess, uint64_t dmisses,
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uint64_t iaccess, uint64_t imisses)
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{
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double dmiss_rate, imiss_rate;
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dmiss_rate = ((double) dmisses) / (daccess) * 100.0;
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imiss_rate = ((double) imisses) / (iaccess) * 100.0;
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g_string_append_printf(line, "%-14lu %-12lu %9.4lf%% %-14lu %-12lu"
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" %9.4lf%%\n",
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daccess,
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dmisses,
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daccess ? dmiss_rate : 0.0,
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iaccess,
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imisses,
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iaccess ? imiss_rate : 0.0);
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}
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static void sum_stats(void)
|
|
{
|
|
int i;
|
|
|
|
g_assert(cores > 1);
|
|
for (i = 0; i < cores; i++) {
|
|
all_imisses += icaches[i]->misses;
|
|
all_dmisses += dcaches[i]->misses;
|
|
all_imem_accesses += icaches[i]->accesses;
|
|
all_dmem_accesses += dcaches[i]->accesses;
|
|
}
|
|
}
|
|
|
|
static int icmp(gconstpointer a, gconstpointer b)
|
|
{
|
|
InsnData *insn_a = (InsnData *) a;
|
|
InsnData *insn_b = (InsnData *) b;
|
|
|
|
return insn_a->imisses < insn_b->imisses ? 1 : -1;
|
|
}
|
|
|
|
static void log_stats(void)
|
|
{
|
|
int i;
|
|
Cache *icache, *dcache;
|
|
|
|
g_autoptr(GString) rep = g_string_new("core #, data accesses, data misses,"
|
|
" dmiss rate, insn accesses,"
|
|
" insn misses, imiss rate\n");
|
|
|
|
for (i = 0; i < cores; i++) {
|
|
g_string_append_printf(rep, "%-8d", i);
|
|
dcache = dcaches[i];
|
|
icache = icaches[i];
|
|
append_stats_line(rep, dcache->accesses, dcache->misses,
|
|
icache->accesses, icache->misses);
|
|
}
|
|
|
|
if (cores > 1) {
|
|
sum_stats();
|
|
g_string_append_printf(rep, "%-8s", "sum");
|
|
append_stats_line(rep, all_dmem_accesses, all_dmisses,
|
|
all_imem_accesses, all_imisses);
|
|
}
|
|
|
|
g_string_append(rep, "\n");
|
|
qemu_plugin_outs(rep->str);
|
|
}
|
|
|
|
static void log_top_insns(void)
|
|
{
|
|
int i;
|
|
GList *curr, *miss_insns;
|
|
InsnData *insn;
|
|
|
|
miss_insns = g_hash_table_get_values(miss_ht);
|
|
miss_insns = g_list_sort(miss_insns, dcmp);
|
|
g_autoptr(GString) rep = g_string_new("");
|
|
g_string_append_printf(rep, "%s", "address, data misses, instruction\n");
|
|
|
|
for (curr = miss_insns, i = 0; curr && i < limit; i++, curr = curr->next) {
|
|
insn = (InsnData *) curr->data;
|
|
g_string_append_printf(rep, "0x%" PRIx64, insn->addr);
|
|
if (insn->symbol) {
|
|
g_string_append_printf(rep, " (%s)", insn->symbol);
|
|
}
|
|
g_string_append_printf(rep, ", %ld, %s\n", insn->dmisses,
|
|
insn->disas_str);
|
|
}
|
|
|
|
miss_insns = g_list_sort(miss_insns, icmp);
|
|
g_string_append_printf(rep, "%s", "\naddress, fetch misses, instruction\n");
|
|
|
|
for (curr = miss_insns, i = 0; curr && i < limit; i++, curr = curr->next) {
|
|
insn = (InsnData *) curr->data;
|
|
g_string_append_printf(rep, "0x%" PRIx64, insn->addr);
|
|
if (insn->symbol) {
|
|
g_string_append_printf(rep, " (%s)", insn->symbol);
|
|
}
|
|
g_string_append_printf(rep, ", %ld, %s\n", insn->imisses,
|
|
insn->disas_str);
|
|
}
|
|
|
|
qemu_plugin_outs(rep->str);
|
|
g_list_free(miss_insns);
|
|
}
|
|
|
|
static void plugin_exit(qemu_plugin_id_t id, void *p)
|
|
{
|
|
log_stats();
|
|
log_top_insns();
|
|
|
|
caches_free(dcaches);
|
|
caches_free(icaches);
|
|
|
|
g_hash_table_destroy(miss_ht);
|
|
}
|
|
|
|
static void policy_init(void)
|
|
{
|
|
switch (policy) {
|
|
case LRU:
|
|
update_hit = lru_update_blk;
|
|
update_miss = lru_update_blk;
|
|
metadata_init = lru_priorities_init;
|
|
metadata_destroy = lru_priorities_destroy;
|
|
break;
|
|
case FIFO:
|
|
update_miss = fifo_update_on_miss;
|
|
metadata_init = fifo_init;
|
|
metadata_destroy = fifo_destroy;
|
|
break;
|
|
case RAND:
|
|
rng = g_rand_new();
|
|
break;
|
|
default:
|
|
g_assert_not_reached();
|
|
}
|
|
}
|
|
|
|
QEMU_PLUGIN_EXPORT
|
|
int qemu_plugin_install(qemu_plugin_id_t id, const qemu_info_t *info,
|
|
int argc, char **argv)
|
|
{
|
|
int i;
|
|
int iassoc, iblksize, icachesize;
|
|
int dassoc, dblksize, dcachesize;
|
|
|
|
limit = 32;
|
|
sys = info->system_emulation;
|
|
|
|
dassoc = 8;
|
|
dblksize = 64;
|
|
dcachesize = dblksize * dassoc * 32;
|
|
|
|
iassoc = 8;
|
|
iblksize = 64;
|
|
icachesize = iblksize * iassoc * 32;
|
|
|
|
policy = LRU;
|
|
|
|
cores = sys ? qemu_plugin_n_vcpus() : 1;
|
|
|
|
for (i = 0; i < argc; i++) {
|
|
char *opt = argv[i];
|
|
if (g_str_has_prefix(opt, "iblksize=")) {
|
|
iblksize = g_ascii_strtoll(opt + 9, NULL, 10);
|
|
} else if (g_str_has_prefix(opt, "iassoc=")) {
|
|
iassoc = g_ascii_strtoll(opt + 7, NULL, 10);
|
|
} else if (g_str_has_prefix(opt, "icachesize=")) {
|
|
icachesize = g_ascii_strtoll(opt + 11, NULL, 10);
|
|
} else if (g_str_has_prefix(opt, "dblksize=")) {
|
|
dblksize = g_ascii_strtoll(opt + 9, NULL, 10);
|
|
} else if (g_str_has_prefix(opt, "dassoc=")) {
|
|
dassoc = g_ascii_strtoll(opt + 7, NULL, 10);
|
|
} else if (g_str_has_prefix(opt, "dcachesize=")) {
|
|
dcachesize = g_ascii_strtoll(opt + 11, NULL, 10);
|
|
} else if (g_str_has_prefix(opt, "limit=")) {
|
|
limit = g_ascii_strtoll(opt + 6, NULL, 10);
|
|
} else if (g_str_has_prefix(opt, "cores=")) {
|
|
cores = g_ascii_strtoll(opt + 6, NULL, 10);
|
|
} else if (g_str_has_prefix(opt, "evict=")) {
|
|
gchar *p = opt + 6;
|
|
if (g_strcmp0(p, "rand") == 0) {
|
|
policy = RAND;
|
|
} else if (g_strcmp0(p, "lru") == 0) {
|
|
policy = LRU;
|
|
} else if (g_strcmp0(p, "fifo") == 0) {
|
|
policy = FIFO;
|
|
} else {
|
|
fprintf(stderr, "invalid eviction policy: %s\n", opt);
|
|
return -1;
|
|
}
|
|
} else {
|
|
fprintf(stderr, "option parsing failed: %s\n", opt);
|
|
return -1;
|
|
}
|
|
}
|
|
|
|
policy_init();
|
|
|
|
dcaches = caches_init(dblksize, dassoc, dcachesize);
|
|
if (!dcaches) {
|
|
const char *err = cache_config_error(dblksize, dassoc, dcachesize);
|
|
fprintf(stderr, "dcache cannot be constructed from given parameters\n");
|
|
fprintf(stderr, "%s\n", err);
|
|
return -1;
|
|
}
|
|
|
|
icaches = caches_init(iblksize, iassoc, icachesize);
|
|
if (!icaches) {
|
|
const char *err = cache_config_error(iblksize, iassoc, icachesize);
|
|
fprintf(stderr, "icache cannot be constructed from given parameters\n");
|
|
fprintf(stderr, "%s\n", err);
|
|
return -1;
|
|
}
|
|
|
|
dcache_locks = g_new0(GMutex, cores);
|
|
icache_locks = g_new0(GMutex, cores);
|
|
|
|
qemu_plugin_register_vcpu_tb_trans_cb(id, vcpu_tb_trans);
|
|
qemu_plugin_register_atexit_cb(id, plugin_exit, NULL);
|
|
|
|
miss_ht = g_hash_table_new_full(NULL, g_direct_equal, NULL, insn_free);
|
|
|
|
return 0;
|
|
}
|