Control view is used to access the ITC Storage Cell Tags. It never causes the issuing thread to block. Guest can empty the FIFO cell by setting Empty bit to 1. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
319 lines
8.4 KiB
C
319 lines
8.4 KiB
C
/*
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* Inter-Thread Communication Unit emulation.
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*
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* Copyright (c) 2016 Imagination Technologies
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/hw.h"
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#include "hw/sysbus.h"
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#include "sysemu/sysemu.h"
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#include "hw/misc/mips_itu.h"
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#define ITC_TAG_ADDRSPACE_SZ (ITC_ADDRESSMAP_NUM * 8)
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/* Initialize as 4kB area to fit all 32 cells with default 128B grain.
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Storage may be resized by the software. */
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#define ITC_STORAGE_ADDRSPACE_SZ 0x1000
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#define ITC_FIFO_NUM_MAX 16
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#define ITC_SEMAPH_NUM_MAX 16
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#define ITC_AM1_NUMENTRIES_OFS 20
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#define ITC_CELL_TAG_FIFO_DEPTH 28
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#define ITC_CELL_TAG_FIFO_PTR 18
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#define ITC_CELL_TAG_FIFO 17
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#define ITC_CELL_TAG_T 16
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#define ITC_CELL_TAG_F 1
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#define ITC_CELL_TAG_E 0
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#define ITC_AM0_BASE_ADDRESS_MASK 0xFFFFFC00ULL
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#define ITC_AM0_EN_MASK 0x1
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#define ITC_AM1_ADDR_MASK_MASK 0x1FC00
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#define ITC_AM1_ENTRY_GRAIN_MASK 0x7
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typedef enum ITCView {
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ITCVIEW_BYPASS = 0,
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ITCVIEW_CONTROL = 1,
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ITCVIEW_EF_SYNC = 2,
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ITCVIEW_EF_TRY = 3,
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ITCVIEW_PV_SYNC = 4,
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ITCVIEW_PV_TRY = 5
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} ITCView;
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MemoryRegion *mips_itu_get_tag_region(MIPSITUState *itu)
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{
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return &itu->tag_io;
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}
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static uint64_t itc_tag_read(void *opaque, hwaddr addr, unsigned size)
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{
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MIPSITUState *tag = (MIPSITUState *)opaque;
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uint64_t index = addr >> 3;
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uint64_t ret = 0;
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switch (index) {
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case 0 ... ITC_ADDRESSMAP_NUM:
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ret = tag->ITCAddressMap[index];
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "Read 0x%" PRIx64 "\n", addr);
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break;
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}
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return ret;
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}
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static void itc_reconfigure(MIPSITUState *tag)
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{
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uint64_t *am = &tag->ITCAddressMap[0];
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MemoryRegion *mr = &tag->storage_io;
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hwaddr address = am[0] & ITC_AM0_BASE_ADDRESS_MASK;
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uint64_t size = (1 << 10) + (am[1] & ITC_AM1_ADDR_MASK_MASK);
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bool is_enabled = (am[0] & ITC_AM0_EN_MASK) != 0;
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memory_region_transaction_begin();
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if (!(size & (size - 1))) {
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memory_region_set_size(mr, size);
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}
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memory_region_set_address(mr, address);
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memory_region_set_enabled(mr, is_enabled);
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memory_region_transaction_commit();
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}
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static void itc_tag_write(void *opaque, hwaddr addr,
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uint64_t data, unsigned size)
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{
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MIPSITUState *tag = (MIPSITUState *)opaque;
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uint64_t *am = &tag->ITCAddressMap[0];
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uint64_t am_old, mask;
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uint64_t index = addr >> 3;
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switch (index) {
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case 0:
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mask = ITC_AM0_BASE_ADDRESS_MASK | ITC_AM0_EN_MASK;
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break;
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case 1:
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mask = ITC_AM1_ADDR_MASK_MASK | ITC_AM1_ENTRY_GRAIN_MASK;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "Bad write 0x%" PRIx64 "\n", addr);
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return;
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}
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am_old = am[index];
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am[index] = (data & mask) | (am_old & ~mask);
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if (am_old != am[index]) {
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itc_reconfigure(tag);
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}
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}
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static const MemoryRegionOps itc_tag_ops = {
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.read = itc_tag_read,
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.write = itc_tag_write,
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.impl = {
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.max_access_size = 8,
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static inline uint32_t get_num_cells(MIPSITUState *s)
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{
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return s->num_fifo + s->num_semaphores;
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}
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static inline ITCView get_itc_view(hwaddr addr)
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{
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return (addr >> 3) & 0xf;
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}
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static inline int get_cell_stride_shift(const MIPSITUState *s)
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{
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/* Minimum interval (for EntryGain = 0) is 128 B */
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return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK);
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}
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static inline ITCStorageCell *get_cell(MIPSITUState *s,
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hwaddr addr)
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{
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uint32_t cell_idx = addr >> get_cell_stride_shift(s);
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uint32_t num_cells = get_num_cells(s);
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if (cell_idx >= num_cells) {
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cell_idx = num_cells - 1;
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}
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return &s->cell[cell_idx];
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}
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/* ITC Control View */
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static inline uint64_t view_control_read(ITCStorageCell *c)
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{
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return ((uint64_t)c->tag.FIFODepth << ITC_CELL_TAG_FIFO_DEPTH) |
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(c->tag.FIFOPtr << ITC_CELL_TAG_FIFO_PTR) |
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(c->tag.FIFO << ITC_CELL_TAG_FIFO) |
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(c->tag.T << ITC_CELL_TAG_T) |
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(c->tag.E << ITC_CELL_TAG_E) |
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(c->tag.F << ITC_CELL_TAG_F);
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}
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static inline void view_control_write(ITCStorageCell *c, uint64_t val)
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{
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c->tag.T = (val >> ITC_CELL_TAG_T) & 1;
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c->tag.E = (val >> ITC_CELL_TAG_E) & 1;
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c->tag.F = (val >> ITC_CELL_TAG_F) & 1;
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if (c->tag.E) {
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c->tag.FIFOPtr = 0;
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}
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}
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static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size)
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{
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MIPSITUState *s = (MIPSITUState *)opaque;
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ITCStorageCell *cell = get_cell(s, addr);
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ITCView view = get_itc_view(addr);
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uint64_t ret = -1;
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switch (view) {
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case ITCVIEW_CONTROL:
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ret = view_control_read(cell);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"itc_storage_read: Bad ITC View %d\n", (int)view);
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break;
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}
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return ret;
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}
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static void itc_storage_write(void *opaque, hwaddr addr, uint64_t data,
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unsigned size)
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{
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MIPSITUState *s = (MIPSITUState *)opaque;
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ITCStorageCell *cell = get_cell(s, addr);
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ITCView view = get_itc_view(addr);
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switch (view) {
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case ITCVIEW_CONTROL:
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view_control_write(cell, data);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"itc_storage_write: Bad ITC View %d\n", (int)view);
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break;
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}
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}
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static const MemoryRegionOps itc_storage_ops = {
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.read = itc_storage_read,
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.write = itc_storage_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void itc_reset_cells(MIPSITUState *s)
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{
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int i;
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memset(s->cell, 0, get_num_cells(s) * sizeof(s->cell[0]));
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for (i = 0; i < s->num_fifo; i++) {
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s->cell[i].tag.E = 1;
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s->cell[i].tag.FIFO = 1;
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s->cell[i].tag.FIFODepth = ITC_CELL_DEPTH_SHIFT;
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}
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}
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static void mips_itu_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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MIPSITUState *s = MIPS_ITU(obj);
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memory_region_init_io(&s->storage_io, OBJECT(s), &itc_storage_ops, s,
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"mips-itc-storage", ITC_STORAGE_ADDRSPACE_SZ);
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sysbus_init_mmio(sbd, &s->storage_io);
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memory_region_init_io(&s->tag_io, OBJECT(s), &itc_tag_ops, s,
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"mips-itc-tag", ITC_TAG_ADDRSPACE_SZ);
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}
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static void mips_itu_realize(DeviceState *dev, Error **errp)
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{
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MIPSITUState *s = MIPS_ITU(dev);
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if (s->num_fifo > ITC_FIFO_NUM_MAX) {
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error_setg(errp, "Exceed maximum number of FIFO cells: %d",
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s->num_fifo);
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return;
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}
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if (s->num_semaphores > ITC_SEMAPH_NUM_MAX) {
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error_setg(errp, "Exceed maximum number of Semaphore cells: %d",
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s->num_semaphores);
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return;
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}
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s->cell = g_new(ITCStorageCell, get_num_cells(s));
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}
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static void mips_itu_reset(DeviceState *dev)
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{
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MIPSITUState *s = MIPS_ITU(dev);
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s->ITCAddressMap[0] = 0;
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s->ITCAddressMap[1] =
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((ITC_STORAGE_ADDRSPACE_SZ - 1) & ITC_AM1_ADDR_MASK_MASK) |
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(get_num_cells(s) << ITC_AM1_NUMENTRIES_OFS);
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itc_reconfigure(s);
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itc_reset_cells(s);
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}
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static Property mips_itu_properties[] = {
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DEFINE_PROP_INT32("num-fifo", MIPSITUState, num_fifo,
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ITC_FIFO_NUM_MAX),
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DEFINE_PROP_INT32("num-semaphores", MIPSITUState, num_semaphores,
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ITC_SEMAPH_NUM_MAX),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void mips_itu_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->props = mips_itu_properties;
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dc->realize = mips_itu_realize;
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dc->reset = mips_itu_reset;
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}
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static const TypeInfo mips_itu_info = {
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.name = TYPE_MIPS_ITU,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(MIPSITUState),
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.instance_init = mips_itu_init,
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.class_init = mips_itu_class_init,
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};
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static void mips_itu_register_types(void)
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{
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type_register_static(&mips_itu_info);
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}
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type_init(mips_itu_register_types)
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