* sd: sdhci: Implement basic vendor specific register support * hw/net/imx_fec: Convert debug fprintf() to trace events * target/arm/cpu: adjust virtual time for all KVM arm cpus * Implement configurable descriptor size in ftgmac100 * hw/misc/imx6ul_ccm: Implement non writable bits in CCM registers * target/arm: More Neon decodetree conversion work -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAl7olzoZHHBldGVyLm1h eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3kkqD/9UtCpXnSTQemK5ejuUrhnb LLtth7ce+XHPIoxyEeaAR89umZkooAjFG5ySnZ5QV5b0FxWrcUyK2saDdBKNHhcG En2kWJxebbAbMAw+vvgWx/NgzbpTwGsdYw7h2gmwpJ0RLqjzfMxwXIm4sA3g9kHs d2ymitwiDvAhQZHJzJ3nWZQ4QUJyDueWuHy5mjBEjAmU3R1YkOAzNCJisq3zMzFV 4bLhA48HnqqJc8sfDqiNSk1+NoP9BUhORHtgPmz2V2RVbT6fHsIyP+pAD+vZIPht NmEY86RmCbuNWrPfYSnCaqx86Jj0T5ZghFlfOlKwy+AghebsAjlQmV5QvksjR5NA 1um0usrnsMT5AF0Hmca7wMizc2Y7Dw7OJQC8LYRWhonR78XvLJU3NNL2K+lk5CQa lzoBauYOZdcQcwNue+xBNN6vR1g7H0Qq0Rpq9acpuU5enjn9KV/fOTdfq6Xy5h8G 0MVwKNtH4HuQKVJXFMXKz7eZvguqRn6aKFNa1FYobfyPHX7V9HmRyWo1nKDK2WL6 oJ3QgH6m2Bumd9GGCDyyWWd/iEn8l+zVHaUZkdEB/msMZdjlqtXMX6AzQMvR54Kd Ee2wgli/O01KAfqVhk11+WCV0Xn3sAC0g3/a9Hg4n884Ef42/+pBbSH8/I+HbJiC ETJeogXVMrBH8v4DDrKzsQ== =UmOR -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200616' into staging * hw: arm: Set vendor property for IMX SDHCI emulations * sd: sdhci: Implement basic vendor specific register support * hw/net/imx_fec: Convert debug fprintf() to trace events * target/arm/cpu: adjust virtual time for all KVM arm cpus * Implement configurable descriptor size in ftgmac100 * hw/misc/imx6ul_ccm: Implement non writable bits in CCM registers * target/arm: More Neon decodetree conversion work # gpg: Signature made Tue 16 Jun 2020 10:56:10 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20200616: (23 commits) hw: arm: Set vendor property for IMX SDHCI emulations sd: sdhci: Implement basic vendor specific register support hw/net/imx_fec: Convert debug fprintf() to trace events target/arm/cpu: adjust virtual time for all KVM arm cpus Implement configurable descriptor size in ftgmac100 hw/misc/imx6ul_ccm: Implement non writable bits in CCM registers target/arm: Convert Neon VDUP (scalar) to decodetree target/arm: Convert Neon VTBL, VTBX to decodetree target/arm: Convert Neon VEXT to decodetree target/arm: Convert Neon 2-reg-scalar long multiplies to decodetree target/arm: Convert Neon 2-reg-scalar VQRDMLAH, VQRDMLSH to decodetree target/arm: Convert Neon 2-reg-scalar VQDMULH, VQRDMULH to decodetree target/arm: Convert Neon 2-reg-scalar float multiplies to decodetree target/arm: Convert Neon 2-reg-scalar integer multiplies to decodetree target/arm: Add missing TCG temp free in do_2shift_env_64() target/arm: Add 'static' and 'const' annotations to VSHLL function arrays target/arm: Convert Neon 3-reg-diff polynomial VMULL target/arm: Convert Neon 3-reg-diff saturating doubling multiplies target/arm: Convert Neon 3-reg-diff long multiplies target/arm: Convert Neon 3-reg-diff VABAL, VABDL to decodetree ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # hw/arm/fsl-imx25.c # hw/arm/fsl-imx6.c # hw/arm/fsl-imx6ul.c # hw/arm/fsl-imx7.c
371 lines
13 KiB
C
371 lines
13 KiB
C
/*
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* Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net>
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*
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* i.MX25 SOC emulation.
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*
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* Based on hw/arm/xlnx-zynqmp.c
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*
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* Copyright (C) 2015 Xilinx Inc
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* Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "hw/arm/fsl-imx25.h"
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#include "sysemu/sysemu.h"
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#include "exec/address-spaces.h"
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#include "hw/qdev-properties.h"
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#include "chardev/char.h"
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#define IMX25_ESDHC_CAPABILITIES 0x07e20000
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static void fsl_imx25_init(Object *obj)
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{
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FslIMX25State *s = FSL_IMX25(obj);
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int i;
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object_initialize_child(obj, "cpu", &s->cpu, ARM_CPU_TYPE_NAME("arm926"));
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object_initialize_child(obj, "avic", &s->avic, TYPE_IMX_AVIC);
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object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX25_CCM);
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for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) {
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object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_IMX_SERIAL);
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}
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for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) {
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object_initialize_child(obj, "gpt[*]", &s->gpt[i], TYPE_IMX25_GPT);
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}
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for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) {
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object_initialize_child(obj, "epit[*]", &s->epit[i], TYPE_IMX_EPIT);
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}
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object_initialize_child(obj, "fec", &s->fec, TYPE_IMX_FEC);
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object_initialize_child(obj, "rngc", &s->rngc, TYPE_IMX_RNGC);
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for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
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object_initialize_child(obj, "i2c[*]", &s->i2c[i], TYPE_IMX_I2C);
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}
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for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) {
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object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_IMX_GPIO);
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}
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for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) {
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object_initialize_child(obj, "sdhc[*]", &s->esdhc[i], TYPE_IMX_USDHC);
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}
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for (i = 0; i < FSL_IMX25_NUM_USBS; i++) {
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object_initialize_child(obj, "usb[*]", &s->usb[i], TYPE_CHIPIDEA);
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}
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object_initialize_child(obj, "wdt", &s->wdt, TYPE_IMX2_WDT);
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}
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static void fsl_imx25_realize(DeviceState *dev, Error **errp)
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{
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FslIMX25State *s = FSL_IMX25(dev);
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uint8_t i;
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Error *err = NULL;
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qdev_realize(DEVICE(&s->cpu), NULL, &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_realize(SYS_BUS_DEVICE(&s->avic), &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX25_AVIC_ADDR);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0,
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qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,
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qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
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sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX25_CCM_ADDR);
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/* Initialize all UARTs */
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for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) {
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static const struct {
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hwaddr addr;
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unsigned int irq;
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} serial_table[FSL_IMX25_NUM_UARTS] = {
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{ FSL_IMX25_UART1_ADDR, FSL_IMX25_UART1_IRQ },
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{ FSL_IMX25_UART2_ADDR, FSL_IMX25_UART2_IRQ },
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{ FSL_IMX25_UART3_ADDR, FSL_IMX25_UART3_IRQ },
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{ FSL_IMX25_UART4_ADDR, FSL_IMX25_UART4_IRQ },
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{ FSL_IMX25_UART5_ADDR, FSL_IMX25_UART5_IRQ }
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};
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qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
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sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
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qdev_get_gpio_in(DEVICE(&s->avic),
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serial_table[i].irq));
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}
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/* Initialize all GPT timers */
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for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) {
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static const struct {
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hwaddr addr;
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unsigned int irq;
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} gpt_table[FSL_IMX25_NUM_GPTS] = {
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{ FSL_IMX25_GPT1_ADDR, FSL_IMX25_GPT1_IRQ },
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{ FSL_IMX25_GPT2_ADDR, FSL_IMX25_GPT2_IRQ },
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{ FSL_IMX25_GPT3_ADDR, FSL_IMX25_GPT3_IRQ },
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{ FSL_IMX25_GPT4_ADDR, FSL_IMX25_GPT4_IRQ }
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};
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s->gpt[i].ccm = IMX_CCM(&s->ccm);
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sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, gpt_table[i].addr);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
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qdev_get_gpio_in(DEVICE(&s->avic),
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gpt_table[i].irq));
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}
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/* Initialize all EPIT timers */
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for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) {
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static const struct {
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hwaddr addr;
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unsigned int irq;
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} epit_table[FSL_IMX25_NUM_EPITS] = {
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{ FSL_IMX25_EPIT1_ADDR, FSL_IMX25_EPIT1_IRQ },
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{ FSL_IMX25_EPIT2_ADDR, FSL_IMX25_EPIT2_IRQ }
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};
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s->epit[i].ccm = IMX_CCM(&s->ccm);
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sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
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qdev_get_gpio_in(DEVICE(&s->avic),
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epit_table[i].irq));
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}
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qdev_set_nic_properties(DEVICE(&s->fec), &nd_table[0]);
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sysbus_realize(SYS_BUS_DEVICE(&s->fec), &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->fec), 0, FSL_IMX25_FEC_ADDR);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->fec), 0,
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qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_FEC_IRQ));
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sysbus_realize(SYS_BUS_DEVICE(&s->rngc), &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->rngc), 0, FSL_IMX25_RNGC_ADDR);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->rngc), 0,
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qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_RNGC_IRQ));
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/* Initialize all I2C */
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for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
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static const struct {
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hwaddr addr;
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unsigned int irq;
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} i2c_table[FSL_IMX25_NUM_I2CS] = {
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{ FSL_IMX25_I2C1_ADDR, FSL_IMX25_I2C1_IRQ },
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{ FSL_IMX25_I2C2_ADDR, FSL_IMX25_I2C2_IRQ },
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{ FSL_IMX25_I2C3_ADDR, FSL_IMX25_I2C3_IRQ }
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};
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sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
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qdev_get_gpio_in(DEVICE(&s->avic),
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i2c_table[i].irq));
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}
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/* Initialize all GPIOs */
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for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) {
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static const struct {
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hwaddr addr;
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unsigned int irq;
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} gpio_table[FSL_IMX25_NUM_GPIOS] = {
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{ FSL_IMX25_GPIO1_ADDR, FSL_IMX25_GPIO1_IRQ },
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{ FSL_IMX25_GPIO2_ADDR, FSL_IMX25_GPIO2_IRQ },
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{ FSL_IMX25_GPIO3_ADDR, FSL_IMX25_GPIO3_IRQ },
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{ FSL_IMX25_GPIO4_ADDR, FSL_IMX25_GPIO4_IRQ }
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};
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sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
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/* Connect GPIO IRQ to PIC */
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
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qdev_get_gpio_in(DEVICE(&s->avic),
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gpio_table[i].irq));
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}
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/* Initialize all SDHC */
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for (i = 0; i < FSL_IMX25_NUM_ESDHCS; i++) {
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static const struct {
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hwaddr addr;
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unsigned int irq;
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} esdhc_table[FSL_IMX25_NUM_ESDHCS] = {
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{ FSL_IMX25_ESDHC1_ADDR, FSL_IMX25_ESDHC1_IRQ },
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{ FSL_IMX25_ESDHC2_ADDR, FSL_IMX25_ESDHC2_IRQ },
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};
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object_property_set_uint(OBJECT(&s->esdhc[i]), 2, "sd-spec-version",
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&err);
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object_property_set_uint(OBJECT(&s->esdhc[i]), IMX25_ESDHC_CAPABILITIES,
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"capareg", &err);
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object_property_set_uint(OBJECT(&s->esdhc[i]), SDHCI_VENDOR_IMX,
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"vendor", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_realize(SYS_BUS_DEVICE(&s->esdhc[i]), &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0,
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qdev_get_gpio_in(DEVICE(&s->avic),
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esdhc_table[i].irq));
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}
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/* USB */
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for (i = 0; i < FSL_IMX25_NUM_USBS; i++) {
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static const struct {
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hwaddr addr;
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unsigned int irq;
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} usb_table[FSL_IMX25_NUM_USBS] = {
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{ FSL_IMX25_USB1_ADDR, FSL_IMX25_USB1_IRQ },
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{ FSL_IMX25_USB2_ADDR, FSL_IMX25_USB2_IRQ },
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};
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sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_table[i].addr);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
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qdev_get_gpio_in(DEVICE(&s->avic),
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usb_table[i].irq));
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}
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/* Watchdog */
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object_property_set_bool(OBJECT(&s->wdt), true, "pretimeout-support",
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&error_abort);
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sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_abort);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, FSL_IMX25_WDT_ADDR);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt), 0,
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qdev_get_gpio_in(DEVICE(&s->avic),
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FSL_IMX25_WDT_IRQ));
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/* initialize 2 x 16 KB ROM */
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memory_region_init_rom(&s->rom[0], OBJECT(dev), "imx25.rom0",
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FSL_IMX25_ROM0_SIZE, &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM0_ADDR,
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&s->rom[0]);
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memory_region_init_rom(&s->rom[1], OBJECT(dev), "imx25.rom1",
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FSL_IMX25_ROM1_SIZE, &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM1_ADDR,
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&s->rom[1]);
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/* initialize internal RAM (128 KB) */
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memory_region_init_ram(&s->iram, NULL, "imx25.iram", FSL_IMX25_IRAM_SIZE,
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&err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ADDR,
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&s->iram);
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/* internal RAM (128 KB) is aliased over 128 MB - 128 KB */
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memory_region_init_alias(&s->iram_alias, OBJECT(dev), "imx25.iram_alias",
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&s->iram, 0, FSL_IMX25_IRAM_ALIAS_SIZE);
|
|
memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ALIAS_ADDR,
|
|
&s->iram_alias);
|
|
}
|
|
|
|
static void fsl_imx25_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
dc->realize = fsl_imx25_realize;
|
|
dc->desc = "i.MX25 SOC";
|
|
/*
|
|
* Reason: uses serial_hds in realize and the imx25 board does not
|
|
* support multiple CPUs
|
|
*/
|
|
dc->user_creatable = false;
|
|
}
|
|
|
|
static const TypeInfo fsl_imx25_type_info = {
|
|
.name = TYPE_FSL_IMX25,
|
|
.parent = TYPE_DEVICE,
|
|
.instance_size = sizeof(FslIMX25State),
|
|
.instance_init = fsl_imx25_init,
|
|
.class_init = fsl_imx25_class_init,
|
|
};
|
|
|
|
static void fsl_imx25_register_types(void)
|
|
{
|
|
type_register_static(&fsl_imx25_type_info);
|
|
}
|
|
|
|
type_init(fsl_imx25_register_types)
|