allowing support of more than 2 mmu access modes. Add backward compatibility is_user variable in targets code when needed. Implement per target cpu_mmu_index function, avoiding duplicated code and #ifdef TARGET_xxx in softmmu core functions. Implement per target mmu modes definitions. As an example, add PowerPC hypervisor mode definition and Alpha executive and kernel modes definitions. Optimize PowerPC case, precomputing mmu_idx when MSR register changes and using the same definition in code translation code. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3384 c046a42c-6fe2-441c-8c8c-71466251a162
442 lines
11 KiB
C
442 lines
11 KiB
C
/*
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* SH4 emulation
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*
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* Copyright (c) 2005 Samuel Tardieu
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <stdarg.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
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#include <signal.h>
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#include <assert.h>
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#include "cpu.h"
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#include "exec-all.h"
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#if defined(CONFIG_USER_ONLY)
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void do_interrupt (CPUState *env)
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{
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env->exception_index = -1;
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}
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int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
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int mmu_idx, int is_softmmu)
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{
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env->tea = address;
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switch (rw) {
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case 0:
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env->exception_index = 0x0a0;
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break;
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case 1:
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env->exception_index = 0x0c0;
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break;
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case 2:
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env->exception_index = 0x0a0;
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break;
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}
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return 1;
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}
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target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
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{
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return addr;
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}
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#else /* !CONFIG_USER_ONLY */
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#define MMU_OK 0
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#define MMU_ITLB_MISS (-1)
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#define MMU_ITLB_MULTIPLE (-2)
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#define MMU_ITLB_VIOLATION (-3)
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#define MMU_DTLB_MISS_READ (-4)
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#define MMU_DTLB_MISS_WRITE (-5)
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#define MMU_DTLB_INITIAL_WRITE (-6)
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#define MMU_DTLB_VIOLATION_READ (-7)
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#define MMU_DTLB_VIOLATION_WRITE (-8)
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#define MMU_DTLB_MULTIPLE (-9)
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#define MMU_DTLB_MISS (-10)
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void do_interrupt(CPUState * env)
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{
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if (loglevel & CPU_LOG_INT) {
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const char *expname;
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switch (env->exception_index) {
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case 0x0e0:
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expname = "addr_error";
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break;
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case 0x040:
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expname = "tlb_miss";
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break;
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case 0x0a0:
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expname = "tlb_violation";
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break;
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case 0x180:
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expname = "illegal_instruction";
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break;
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case 0x1a0:
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expname = "slot_illegal_instruction";
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break;
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case 0x800:
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expname = "fpu_disable";
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break;
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case 0x820:
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expname = "slot_fpu";
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break;
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case 0x100:
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expname = "data_write";
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break;
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case 0x060:
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expname = "dtlb_miss_write";
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break;
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case 0x0c0:
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expname = "dtlb_violation_write";
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break;
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case 0x120:
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expname = "fpu_exception";
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break;
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case 0x080:
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expname = "initial_page_write";
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break;
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case 0x160:
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expname = "trapa";
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break;
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default:
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expname = "???";
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break;
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}
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fprintf(logfile, "exception 0x%03x [%s] raised\n",
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env->exception_index, expname);
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cpu_dump_state(env, logfile, fprintf, 0);
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}
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env->ssr = env->sr;
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env->spc = env->spc;
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env->sgr = env->gregs[15];
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env->sr |= SR_BL | SR_MD | SR_RB;
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env->expevt = env->exception_index & 0x7ff;
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switch (env->exception_index) {
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case 0x040:
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case 0x060:
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case 0x080:
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env->pc = env->vbr + 0x400;
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break;
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case 0x140:
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env->pc = 0xa0000000;
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break;
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default:
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env->pc = env->vbr + 0x100;
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break;
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}
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}
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static void update_itlb_use(CPUState * env, int itlbnb)
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{
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uint8_t or_mask = 0, and_mask = (uint8_t) - 1;
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switch (itlbnb) {
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case 0:
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and_mask = 0x7f;
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break;
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case 1:
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and_mask = 0xe7;
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or_mask = 0x80;
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break;
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case 2:
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and_mask = 0xfb;
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or_mask = 0x50;
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break;
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case 3:
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or_mask = 0x2c;
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break;
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}
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env->mmucr &= (and_mask << 24);
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env->mmucr |= (or_mask << 24);
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}
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static int itlb_replacement(CPUState * env)
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{
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if ((env->mmucr & 0xe0000000) == 0xe0000000)
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return 0;
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if ((env->mmucr & 0x98000000) == 0x08000000)
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return 1;
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if ((env->mmucr & 0x54000000) == 0x04000000)
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return 2;
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if ((env->mmucr & 0x2c000000) == 0x00000000)
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return 3;
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assert(0);
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}
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/* Find the corresponding entry in the right TLB
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Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
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*/
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static int find_tlb_entry(CPUState * env, target_ulong address,
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tlb_t * entries, uint8_t nbtlb, int use_asid)
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{
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int match = MMU_DTLB_MISS;
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uint32_t start, end;
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uint8_t asid;
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int i;
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asid = env->pteh & 0xff;
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for (i = 0; i < nbtlb; i++) {
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if (!entries[i].v)
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continue; /* Invalid entry */
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if (use_asid && entries[i].asid != asid && !entries[i].sh)
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continue; /* Bad ASID */
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#if 0
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switch (entries[i].sz) {
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case 0:
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size = 1024; /* 1kB */
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break;
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case 1:
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size = 4 * 1024; /* 4kB */
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break;
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case 2:
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size = 64 * 1024; /* 64kB */
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break;
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case 3:
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size = 1024 * 1024; /* 1MB */
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break;
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default:
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assert(0);
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}
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#endif
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start = (entries[i].vpn << 10) & ~(entries[i].size - 1);
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end = start + entries[i].size - 1;
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if (address >= start && address <= end) { /* Match */
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if (match != -1)
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return MMU_DTLB_MULTIPLE; /* Multiple match */
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match = i;
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}
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}
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return match;
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}
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/* Find itlb entry - update itlb from utlb if necessary and asked for
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Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
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Update the itlb from utlb if update is not 0
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*/
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int find_itlb_entry(CPUState * env, target_ulong address,
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int use_asid, int update)
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{
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int e, n;
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e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid);
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if (e == MMU_DTLB_MULTIPLE)
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e = MMU_ITLB_MULTIPLE;
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else if (e == MMU_DTLB_MISS && update) {
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e = find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
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if (e >= 0) {
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n = itlb_replacement(env);
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env->itlb[n] = env->utlb[e];
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e = n;
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}
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}
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if (e >= 0)
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update_itlb_use(env, e);
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return e;
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}
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/* Find utlb entry
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Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
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int find_utlb_entry(CPUState * env, target_ulong address, int use_asid)
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{
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uint8_t urb, urc;
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/* Increment URC */
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urb = ((env->mmucr) >> 18) & 0x3f;
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urc = ((env->mmucr) >> 10) & 0x3f;
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urc++;
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if (urc == urb || urc == UTLB_SIZE - 1)
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urc = 0;
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env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10);
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/* Return entry */
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return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
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}
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/* Match address against MMU
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Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
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MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
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MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
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MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION
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*/
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static int get_mmu_address(CPUState * env, target_ulong * physical,
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int *prot, target_ulong address,
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int rw, int access_type)
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{
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int use_asid, is_code, n;
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tlb_t *matching = NULL;
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use_asid = (env->mmucr & MMUCR_SV) == 0 && (env->sr & SR_MD) == 0;
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is_code = env->pc == address; /* Hack */
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/* Use a hack to find if this is an instruction or data access */
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if (env->pc == address && !(rw & PAGE_WRITE)) {
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n = find_itlb_entry(env, address, use_asid, 1);
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if (n >= 0) {
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matching = &env->itlb[n];
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if ((env->sr & SR_MD) & !(matching->pr & 2))
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n = MMU_ITLB_VIOLATION;
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else
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*prot = PAGE_READ;
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}
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} else {
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n = find_utlb_entry(env, address, use_asid);
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if (n >= 0) {
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matching = &env->utlb[n];
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switch ((matching->pr << 1) | ((env->sr & SR_MD) ? 1 : 0)) {
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case 0: /* 000 */
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case 2: /* 010 */
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n = (rw & PAGE_WRITE) ? MMU_DTLB_VIOLATION_WRITE :
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MMU_DTLB_VIOLATION_READ;
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break;
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case 1: /* 001 */
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case 4: /* 100 */
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case 5: /* 101 */
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if (rw & PAGE_WRITE)
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n = MMU_DTLB_VIOLATION_WRITE;
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else
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*prot = PAGE_READ;
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break;
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case 3: /* 011 */
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case 6: /* 110 */
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case 7: /* 111 */
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*prot = rw & (PAGE_READ | PAGE_WRITE);
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break;
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}
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} else if (n == MMU_DTLB_MISS) {
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n = (rw & PAGE_WRITE) ? MMU_DTLB_MISS_WRITE :
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MMU_DTLB_MISS_READ;
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}
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}
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if (n >= 0) {
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*physical = ((matching->ppn << 10) & ~(matching->size - 1)) |
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(address & (matching->size - 1));
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if ((rw & PAGE_WRITE) & !matching->d)
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n = MMU_DTLB_INITIAL_WRITE;
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else
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n = MMU_OK;
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}
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return n;
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}
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int get_physical_address(CPUState * env, target_ulong * physical,
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int *prot, target_ulong address,
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int rw, int access_type)
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{
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/* P1, P2 and P4 areas do not use translation */
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if ((address >= 0x80000000 && address < 0xc0000000) ||
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address >= 0xe0000000) {
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if (!(env->sr & SR_MD)
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&& (address < 0xe0000000 || address > 0xe4000000)) {
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/* Unauthorized access in user mode (only store queues are available) */
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fprintf(stderr, "Unauthorized access\n");
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return (rw & PAGE_WRITE) ? MMU_DTLB_MISS_WRITE :
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MMU_DTLB_MISS_READ;
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}
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/* Mask upper 3 bits */
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*physical = address & 0x1FFFFFFF;
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*prot = PAGE_READ | PAGE_WRITE;
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return MMU_OK;
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}
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/* If MMU is disabled, return the corresponding physical page */
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if (!env->mmucr & MMUCR_AT) {
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*physical = address & 0x1FFFFFFF;
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*prot = PAGE_READ | PAGE_WRITE;
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return MMU_OK;
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}
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/* We need to resort to the MMU */
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return get_mmu_address(env, physical, prot, address, rw, access_type);
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}
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int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
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int mmu_idx, int is_softmmu)
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{
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target_ulong physical, page_offset, page_size;
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int prot, ret, access_type;
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/* XXXXX */
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#if 0
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fprintf(stderr, "%s pc %08x ad %08x rw %d mmu_idx %d smmu %d\n",
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__func__, env->pc, address, rw, mmu_idx, is_softmmu);
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#endif
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access_type = ACCESS_INT;
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ret =
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get_physical_address(env, &physical, &prot, address, rw,
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access_type);
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if (ret != MMU_OK) {
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env->tea = address;
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switch (ret) {
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case MMU_ITLB_MISS:
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case MMU_DTLB_MISS_READ:
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env->exception_index = 0x040;
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break;
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case MMU_DTLB_MULTIPLE:
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case MMU_ITLB_MULTIPLE:
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env->exception_index = 0x140;
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break;
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case MMU_ITLB_VIOLATION:
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env->exception_index = 0x0a0;
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break;
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case MMU_DTLB_MISS_WRITE:
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env->exception_index = 0x060;
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break;
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case MMU_DTLB_INITIAL_WRITE:
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env->exception_index = 0x080;
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break;
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case MMU_DTLB_VIOLATION_READ:
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env->exception_index = 0x0a0;
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break;
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case MMU_DTLB_VIOLATION_WRITE:
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env->exception_index = 0x0c0;
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break;
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default:
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assert(0);
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}
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return 1;
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}
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page_size = TARGET_PAGE_SIZE;
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page_offset =
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(address - (address & TARGET_PAGE_MASK)) & ~(page_size - 1);
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address = (address & TARGET_PAGE_MASK) + page_offset;
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physical = (physical & TARGET_PAGE_MASK) + page_offset;
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return tlb_set_page(env, address, physical, prot, mmu_idx, is_softmmu);
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}
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target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
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{
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target_ulong physical;
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int prot;
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get_physical_address(env, &physical, &prot, addr, PAGE_READ, 0);
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return physical;
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}
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#endif
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