Introduce a max_cpus per-machine variable, allowing individual boards to limit it's number of CPUs. Check requested number of CPUs in setup code and exit if it exceeds the supported number for the machine. This also renders the static MAX_CPUS check obsolete, so remove this from vl.c. Signed-off-by: Jes Sorensen <jes@sgi.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5443 c046a42c-6fe2-441c-8c8c-71466251a162
612 lines
20 KiB
C
612 lines
20 KiB
C
/*
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* QEMU Sun4u/Sun4v System Emulator
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*
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* Copyright (c) 2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "pci.h"
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#include "pc.h"
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#include "nvram.h"
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#include "fdc.h"
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#include "net.h"
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#include "qemu-timer.h"
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#include "sysemu.h"
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#include "boards.h"
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#include "firmware_abi.h"
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#include "fw_cfg.h"
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//#define DEBUG_IRQ
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#ifdef DEBUG_IRQ
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#define DPRINTF(fmt, args...) \
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do { printf("CPUIRQ: " fmt , ##args); } while (0)
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#else
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#define DPRINTF(fmt, args...)
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#endif
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#define KERNEL_LOAD_ADDR 0x00404000
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#define CMDLINE_ADDR 0x003ff000
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#define INITRD_LOAD_ADDR 0x00300000
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#define PROM_SIZE_MAX (4 * 1024 * 1024)
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#define PROM_VADDR 0x000ffd00000ULL
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#define APB_SPECIAL_BASE 0x1fe00000000ULL
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#define APB_MEM_BASE 0x1ff00000000ULL
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#define VGA_BASE (APB_MEM_BASE + 0x400000ULL)
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#define PROM_FILENAME "openbios-sparc64"
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#define NVRAM_SIZE 0x2000
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#define MAX_IDE_BUS 2
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#define BIOS_CFG_IOPORT 0x510
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#define MAX_PILS 16
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struct hwdef {
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const char * const default_cpu_model;
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uint16_t machine_id;
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uint64_t prom_addr;
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uint64_t console_serial_base;
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};
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int DMA_get_channel_mode (int nchan)
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{
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return 0;
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}
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int DMA_read_memory (int nchan, void *buf, int pos, int size)
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{
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return 0;
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}
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int DMA_write_memory (int nchan, void *buf, int pos, int size)
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{
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return 0;
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}
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void DMA_hold_DREQ (int nchan) {}
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void DMA_release_DREQ (int nchan) {}
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void DMA_schedule(int nchan) {}
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void DMA_run (void) {}
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void DMA_init (int high_page_enable) {}
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void DMA_register_channel (int nchan,
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DMA_transfer_handler transfer_handler,
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void *opaque)
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{
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}
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static int nvram_boot_set(void *opaque, const char *boot_device)
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{
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unsigned int i;
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uint8_t image[sizeof(ohwcfg_v3_t)];
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ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ
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m48t59_t *nvram = (m48t59_t *)opaque;
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for (i = 0; i < sizeof(image); i++)
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image[i] = m48t59_read(nvram, i) & 0xff;
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pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
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boot_device);
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header->nboot_devices = strlen(boot_device) & 0xff;
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header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
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for (i = 0; i < sizeof(image); i++)
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m48t59_write(nvram, i, image[i]);
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return 0;
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}
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static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
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const char *arch,
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ram_addr_t RAM_size,
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const char *boot_devices,
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uint32_t kernel_image, uint32_t kernel_size,
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const char *cmdline,
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uint32_t initrd_image, uint32_t initrd_size,
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uint32_t NVRAM_image,
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int width, int height, int depth,
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const uint8_t *macaddr)
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{
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unsigned int i;
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uint32_t start, end;
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uint8_t image[0x1ff0];
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ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ
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struct sparc_arch_cfg *sparc_header;
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struct OpenBIOS_nvpart_v1 *part_header;
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memset(image, '\0', sizeof(image));
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// Try to match PPC NVRAM
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pstrcpy((char *)header->struct_ident, sizeof(header->struct_ident),
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"QEMU_BIOS");
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header->struct_version = cpu_to_be32(3); /* structure v3 */
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header->nvram_size = cpu_to_be16(NVRAM_size);
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header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
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header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
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pstrcpy((char *)header->arch, sizeof(header->arch), arch);
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header->nb_cpus = smp_cpus & 0xff;
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header->RAM0_base = 0;
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header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
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pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
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boot_devices);
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header->nboot_devices = strlen(boot_devices) & 0xff;
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header->kernel_image = cpu_to_be64((uint64_t)kernel_image);
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header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
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if (cmdline) {
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pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline);
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header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
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header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
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}
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header->initrd_image = cpu_to_be64((uint64_t)initrd_image);
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header->initrd_size = cpu_to_be64((uint64_t)initrd_size);
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header->NVRAM_image = cpu_to_be64((uint64_t)NVRAM_image);
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header->width = cpu_to_be16(width);
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header->height = cpu_to_be16(height);
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header->depth = cpu_to_be16(depth);
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if (nographic)
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header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
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header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
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// Architecture specific header
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start = sizeof(ohwcfg_v3_t);
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sparc_header = (struct sparc_arch_cfg *)&image[start];
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sparc_header->valid = 0;
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start += sizeof(struct sparc_arch_cfg);
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// OpenBIOS nvram variables
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// Variable partition
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part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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part_header->signature = OPENBIOS_PART_SYSTEM;
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pstrcpy(part_header->name, sizeof(part_header->name), "system");
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end = start + sizeof(struct OpenBIOS_nvpart_v1);
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for (i = 0; i < nb_prom_envs; i++)
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end = OpenBIOS_set_var(image, end, prom_envs[i]);
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// End marker
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image[end++] = '\0';
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end = start + ((end - start + 15) & ~15);
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OpenBIOS_finish_partition(part_header, end - start);
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// free partition
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start = end;
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part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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part_header->signature = OPENBIOS_PART_FREE;
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pstrcpy(part_header->name, sizeof(part_header->name), "free");
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end = 0x1fd0;
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OpenBIOS_finish_partition(part_header, end - start);
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Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
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for (i = 0; i < sizeof(image); i++)
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m48t59_write(nvram, i, image[i]);
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qemu_register_boot_set(nvram_boot_set, nvram);
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return 0;
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}
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void pic_info(void)
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{
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}
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void irq_info(void)
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{
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}
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void cpu_check_irqs(CPUState *env)
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{
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uint32_t pil = env->pil_in | (env->softint & ~SOFTINT_TIMER) |
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((env->softint & SOFTINT_TIMER) << 14);
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if (pil && (env->interrupt_index == 0 ||
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(env->interrupt_index & ~15) == TT_EXTINT)) {
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unsigned int i;
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for (i = 15; i > 0; i--) {
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if (pil & (1 << i)) {
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int old_interrupt = env->interrupt_index;
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env->interrupt_index = TT_EXTINT | i;
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if (old_interrupt != env->interrupt_index) {
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DPRINTF("Set CPU IRQ %d\n", i);
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cpu_interrupt(env, CPU_INTERRUPT_HARD);
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}
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break;
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}
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}
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} else if (!pil && (env->interrupt_index & ~15) == TT_EXTINT) {
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DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
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env->interrupt_index = 0;
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
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}
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}
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static void cpu_set_irq(void *opaque, int irq, int level)
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{
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CPUState *env = opaque;
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if (level) {
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DPRINTF("Raise CPU IRQ %d\n", irq);
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env->halted = 0;
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env->pil_in |= 1 << irq;
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cpu_check_irqs(env);
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} else {
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DPRINTF("Lower CPU IRQ %d\n", irq);
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env->pil_in &= ~(1 << irq);
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cpu_check_irqs(env);
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}
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}
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void qemu_system_powerdown(void)
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{
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}
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typedef struct ResetData {
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CPUState *env;
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uint64_t reset_addr;
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} ResetData;
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static void main_cpu_reset(void *opaque)
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{
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ResetData *s = (ResetData *)opaque;
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CPUState *env = s->env;
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cpu_reset(env);
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ptimer_set_limit(env->tick, 0x7fffffffffffffffULL, 1);
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ptimer_run(env->tick, 0);
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ptimer_set_limit(env->stick, 0x7fffffffffffffffULL, 1);
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ptimer_run(env->stick, 0);
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ptimer_set_limit(env->hstick, 0x7fffffffffffffffULL, 1);
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ptimer_run(env->hstick, 0);
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env->gregs[1] = 0; // Memory start
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env->gregs[2] = ram_size; // Memory size
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env->gregs[3] = 0; // Machine description XXX
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env->pc = s->reset_addr;
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env->npc = env->pc + 4;
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}
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static void tick_irq(void *opaque)
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{
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CPUState *env = opaque;
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env->softint |= SOFTINT_TIMER;
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cpu_interrupt(env, CPU_INTERRUPT_TIMER);
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}
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static void stick_irq(void *opaque)
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{
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CPUState *env = opaque;
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env->softint |= SOFTINT_TIMER;
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cpu_interrupt(env, CPU_INTERRUPT_TIMER);
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}
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static void hstick_irq(void *opaque)
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{
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CPUState *env = opaque;
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env->softint |= SOFTINT_TIMER;
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cpu_interrupt(env, CPU_INTERRUPT_TIMER);
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}
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void cpu_tick_set_count(void *opaque, uint64_t count)
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{
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ptimer_set_count(opaque, -count);
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}
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uint64_t cpu_tick_get_count(void *opaque)
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{
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return -ptimer_get_count(opaque);
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}
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void cpu_tick_set_limit(void *opaque, uint64_t limit)
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{
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ptimer_set_limit(opaque, -limit, 0);
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}
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static const int ide_iobase[2] = { 0x1f0, 0x170 };
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static const int ide_iobase2[2] = { 0x3f6, 0x376 };
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static const int ide_irq[2] = { 14, 15 };
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static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
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static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
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static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
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static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
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static fdctrl_t *floppy_controller;
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static void sun4uv_init(ram_addr_t RAM_size, int vga_ram_size,
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const char *boot_devices, DisplayState *ds,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model,
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const struct hwdef *hwdef)
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{
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CPUState *env;
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char buf[1024];
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m48t59_t *nvram;
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int ret, linux_boot;
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unsigned int i;
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long prom_offset, initrd_size, kernel_size;
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PCIBus *pci_bus;
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QEMUBH *bh;
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qemu_irq *irq;
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int drive_index;
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BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
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BlockDriverState *fd[MAX_FD];
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void *fw_cfg;
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ResetData *reset_info;
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linux_boot = (kernel_filename != NULL);
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/* init CPUs */
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if (!cpu_model)
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cpu_model = hwdef->default_cpu_model;
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env = cpu_init(cpu_model);
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if (!env) {
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fprintf(stderr, "Unable to find Sparc CPU definition\n");
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exit(1);
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}
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bh = qemu_bh_new(tick_irq, env);
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env->tick = ptimer_init(bh);
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ptimer_set_period(env->tick, 1ULL);
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bh = qemu_bh_new(stick_irq, env);
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env->stick = ptimer_init(bh);
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ptimer_set_period(env->stick, 1ULL);
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bh = qemu_bh_new(hstick_irq, env);
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env->hstick = ptimer_init(bh);
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ptimer_set_period(env->hstick, 1ULL);
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reset_info = qemu_mallocz(sizeof(ResetData));
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reset_info->env = env;
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reset_info->reset_addr = hwdef->prom_addr + 0x40ULL;
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qemu_register_reset(main_cpu_reset, reset_info);
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main_cpu_reset(reset_info);
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// Override warm reset address with cold start address
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env->pc = hwdef->prom_addr + 0x20ULL;
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env->npc = env->pc + 4;
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/* allocate RAM */
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cpu_register_physical_memory(0, RAM_size, 0);
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prom_offset = RAM_size + vga_ram_size;
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cpu_register_physical_memory(hwdef->prom_addr,
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(PROM_SIZE_MAX + TARGET_PAGE_SIZE) &
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TARGET_PAGE_MASK,
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prom_offset | IO_MEM_ROM);
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if (bios_name == NULL)
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bios_name = PROM_FILENAME;
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
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ret = load_elf(buf, hwdef->prom_addr - PROM_VADDR, NULL, NULL, NULL);
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if (ret < 0) {
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ret = load_image_targphys(buf, hwdef->prom_addr,
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(PROM_SIZE_MAX + TARGET_PAGE_SIZE) &
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TARGET_PAGE_MASK);
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if (ret < 0) {
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fprintf(stderr, "qemu: could not load prom '%s'\n",
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buf);
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exit(1);
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}
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}
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kernel_size = 0;
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initrd_size = 0;
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if (linux_boot) {
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/* XXX: put correct offset */
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kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL);
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if (kernel_size < 0)
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kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
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ram_size - KERNEL_LOAD_ADDR);
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if (kernel_size < 0)
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kernel_size = load_image_targphys(kernel_filename,
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KERNEL_LOAD_ADDR,
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ram_size - KERNEL_LOAD_ADDR);
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if (kernel_size < 0) {
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fprintf(stderr, "qemu: could not load kernel '%s'\n",
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kernel_filename);
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exit(1);
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}
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/* load initrd */
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if (initrd_filename) {
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initrd_size = load_image_targphys(initrd_filename,
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INITRD_LOAD_ADDR,
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ram_size - INITRD_LOAD_ADDR);
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if (initrd_size < 0) {
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fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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initrd_filename);
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exit(1);
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}
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}
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if (initrd_size > 0) {
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for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
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if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
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stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
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stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
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break;
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}
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}
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}
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}
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pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
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isa_mem_base = VGA_BASE;
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pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + RAM_size, RAM_size,
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vga_ram_size);
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i = 0;
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if (hwdef->console_serial_base) {
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serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200,
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serial_hds[i], 1);
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i++;
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}
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for(; i < MAX_SERIAL_PORTS; i++) {
|
|
if (serial_hds[i]) {
|
|
serial_init(serial_io[i], NULL/*serial_irq[i]*/, 115200,
|
|
serial_hds[i]);
|
|
}
|
|
}
|
|
|
|
for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
|
|
if (parallel_hds[i]) {
|
|
parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/,
|
|
parallel_hds[i]);
|
|
}
|
|
}
|
|
|
|
for(i = 0; i < nb_nics; i++) {
|
|
if (!nd_table[i].model)
|
|
nd_table[i].model = "ne2k_pci";
|
|
pci_nic_init(pci_bus, &nd_table[i], -1);
|
|
}
|
|
|
|
irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
|
|
if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
|
|
fprintf(stderr, "qemu: too many IDE bus\n");
|
|
exit(1);
|
|
}
|
|
for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
|
|
drive_index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS,
|
|
i % MAX_IDE_DEVS);
|
|
if (drive_index != -1)
|
|
hd[i] = drives_table[drive_index].bdrv;
|
|
else
|
|
hd[i] = NULL;
|
|
}
|
|
|
|
// XXX pci_cmd646_ide_init(pci_bus, hd, 1);
|
|
pci_piix3_ide_init(pci_bus, hd, -1, irq);
|
|
/* FIXME: wire up interrupts. */
|
|
i8042_init(NULL/*1*/, NULL/*12*/, 0x60);
|
|
for(i = 0; i < MAX_FD; i++) {
|
|
drive_index = drive_get_index(IF_FLOPPY, 0, i);
|
|
if (drive_index != -1)
|
|
fd[i] = drives_table[drive_index].bdrv;
|
|
else
|
|
fd[i] = NULL;
|
|
}
|
|
floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd);
|
|
nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59);
|
|
sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
|
|
KERNEL_LOAD_ADDR, kernel_size,
|
|
kernel_cmdline,
|
|
INITRD_LOAD_ADDR, initrd_size,
|
|
/* XXX: need an option to load a NVRAM image */
|
|
0,
|
|
graphic_width, graphic_height, graphic_depth,
|
|
(uint8_t *)&nd_table[0].macaddr);
|
|
|
|
fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
|
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
|
|
}
|
|
|
|
enum {
|
|
sun4u_id = 0,
|
|
sun4v_id = 64,
|
|
niagara_id,
|
|
};
|
|
|
|
static const struct hwdef hwdefs[] = {
|
|
/* Sun4u generic PC-like machine */
|
|
{
|
|
.default_cpu_model = "TI UltraSparc II",
|
|
.machine_id = sun4u_id,
|
|
.prom_addr = 0x1fff0000000ULL,
|
|
.console_serial_base = 0,
|
|
},
|
|
/* Sun4v generic PC-like machine */
|
|
{
|
|
.default_cpu_model = "Sun UltraSparc T1",
|
|
.machine_id = sun4v_id,
|
|
.prom_addr = 0x1fff0000000ULL,
|
|
.console_serial_base = 0,
|
|
},
|
|
/* Sun4v generic Niagara machine */
|
|
{
|
|
.default_cpu_model = "Sun UltraSparc T1",
|
|
.machine_id = niagara_id,
|
|
.prom_addr = 0xfff0000000ULL,
|
|
.console_serial_base = 0xfff0c2c000ULL,
|
|
},
|
|
};
|
|
|
|
/* Sun4u hardware initialisation */
|
|
static void sun4u_init(ram_addr_t RAM_size, int vga_ram_size,
|
|
const char *boot_devices, DisplayState *ds,
|
|
const char *kernel_filename, const char *kernel_cmdline,
|
|
const char *initrd_filename, const char *cpu_model)
|
|
{
|
|
sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename,
|
|
kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
|
|
}
|
|
|
|
/* Sun4v hardware initialisation */
|
|
static void sun4v_init(ram_addr_t RAM_size, int vga_ram_size,
|
|
const char *boot_devices, DisplayState *ds,
|
|
const char *kernel_filename, const char *kernel_cmdline,
|
|
const char *initrd_filename, const char *cpu_model)
|
|
{
|
|
sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename,
|
|
kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
|
|
}
|
|
|
|
/* Niagara hardware initialisation */
|
|
static void niagara_init(ram_addr_t RAM_size, int vga_ram_size,
|
|
const char *boot_devices, DisplayState *ds,
|
|
const char *kernel_filename, const char *kernel_cmdline,
|
|
const char *initrd_filename, const char *cpu_model)
|
|
{
|
|
sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename,
|
|
kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
|
|
}
|
|
|
|
QEMUMachine sun4u_machine = {
|
|
.name = "sun4u",
|
|
.desc = "Sun4u platform",
|
|
.init = sun4u_init,
|
|
.ram_require = PROM_SIZE_MAX + VGA_RAM_SIZE,
|
|
.nodisk_ok = 1,
|
|
.max_cpus = 16,
|
|
};
|
|
|
|
QEMUMachine sun4v_machine = {
|
|
.name = "sun4v",
|
|
.desc = "Sun4v platform",
|
|
.init = sun4v_init,
|
|
.ram_require = PROM_SIZE_MAX + VGA_RAM_SIZE,
|
|
.nodisk_ok = 1,
|
|
.max_cpus = 16,
|
|
};
|
|
|
|
QEMUMachine niagara_machine = {
|
|
.name = "Niagara",
|
|
.desc = "Sun4v platform, Niagara",
|
|
.init = niagara_init,
|
|
.ram_require = PROM_SIZE_MAX + VGA_RAM_SIZE,
|
|
.nodisk_ok = 1,
|
|
.max_cpus = 16,
|
|
};
|