fcf5ef2ab5
We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part] Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part] Acked-by: Michael Walle <michael@walle.cc> [lm32 part] Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part] Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part] Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part] Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part] Acked-by: Richard Henderson <rth@twiddle.net> [alpha part] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part] Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [crisµblaze part] Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part] Signed-off-by: Thomas Huth <thuth@redhat.com>
56 lines
2.4 KiB
Modula-2
56 lines
2.4 KiB
Modula-2
/* Description of s390 insn formats. */
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/* NAME F1, F2... */
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F0(E)
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F1(I, I(1, 8, 8))
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F2(RI_a, R(1, 8), I(2,16,16))
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F2(RI_b, R(1, 8), I(2,16,16))
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F2(RI_c, M(1, 8), I(2,16,16))
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F3(RIE_a, R(1, 8), I(2,16,16), M(3,32))
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F4(RIE_b, R(1, 8), R(2,12), M(3,32), I(4,16,16))
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F4(RIE_c, R(1, 8), I(2,32, 8), M(3,12), I(4,16,16))
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F3(RIE_d, R(1, 8), I(2,16,16), R(3,12))
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F3(RIE_e, R(1, 8), I(2,16,16), R(3,12))
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F5(RIE_f, R(1, 8), R(2,12), I(3,16,8), I(4,24,8), I(5,32,8))
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F2(RIL_a, R(1, 8), I(2,16,32))
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F2(RIL_b, R(1, 8), I(2,16,32))
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F2(RIL_c, M(1, 8), I(2,16,32))
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F4(RIS, R(1, 8), I(2,32, 8), M(3,12), BD(4,16,20))
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/* ??? The PoO does not call out subtypes _a and _b for RR, as it does
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for e.g. RX. Our checking requires this for e.g. BCR. */
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F2(RR_a, R(1, 8), R(2,12))
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F2(RR_b, M(1, 8), R(2,12))
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F2(RRE, R(1,24), R(2,28))
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F3(RRD, R(1,16), R(2,28), R(3,24))
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F4(RRF_a, R(1,24), R(2,28), R(3,16), M(4,20))
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F4(RRF_b, R(1,24), R(2,28), R(3,16), M(4,20))
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F4(RRF_c, R(1,24), R(2,28), M(3,16), M(4,20))
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F4(RRF_d, R(1,24), R(2,28), M(3,16), M(4,20))
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F4(RRF_e, R(1,24), R(2,28), M(3,16), M(4,20))
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F4(RRS, R(1, 8), R(2,12), M(3,32), BD(4,16,20))
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F3(RS_a, R(1, 8), BD(2,16,20), R(3,12))
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F3(RS_b, R(1, 8), BD(2,16,20), M(3,12))
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F3(RSI, R(1, 8), I(2,16,16), R(3,12))
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F2(RSL, L(1, 8, 4), BD(1,16,20))
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F3(RSY_a, R(1, 8), BDL(2), R(3,12))
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F3(RSY_b, R(1, 8), BDL(2), M(3,12))
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F2(RX_a, R(1, 8), BXD(2))
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F2(RX_b, M(1, 8), BXD(2))
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F2(RXE, R(1, 8), BXD(2))
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F3(RXF, R(1,32), BXD(2), R(3, 8))
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F2(RXY_a, R(1, 8), BXDL(2))
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F2(RXY_b, M(1, 8), BXDL(2))
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F1(S, BD(2,16,20))
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F2(SI, BD(1,16,20), I(2,8,8))
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F2(SIL, BD(1,16,20), I(2,32,16))
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F2(SIY, BDL(1), I(2, 8, 8))
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F3(SS_a, L(1, 8, 8), BD(1,16,20), BD(2,32,36))
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F4(SS_b, L(1, 8, 4), BD(1,16,20), L(2,12,4), BD(2,32,36))
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F4(SS_c, L(1, 8, 4), BD(1,16,20), BD(2,32,36), I(3,12, 4))
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/* ??? Odd man out. The L1 field here is really a register, but the
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easy way to compress the fields has R1 and B1 overlap. */
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F4(SS_d, L(1, 8, 4), BD(1,16,20), BD(2,32,36), R(3,12))
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F4(SS_e, R(1, 8), BD(2,16,20), R(3,12), BD(4,32,36))
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F3(SS_f, BD(1,16,20), L(2,8,8), BD(2,32,36))
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F2(SSE, BD(1,16,20), BD(2,32,36))
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F3(SSF, BD(1,16,20), BD(2,32,36), R(3,8))
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