Record the software fp control register, as set by the osf_setsysinfo syscall. Add those masked exceptions to fpcr_exc_enable. Do not raise a signal for masked fp exceptions. Fixes: https://bugs.launchpad.net/bugs/1701835 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
569 lines
14 KiB
C
569 lines
14 KiB
C
/*
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* Helpers for floating point instructions.
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*
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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#include "fpu/softfloat.h"
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#define FP_STATUS (env->fp_status)
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void helper_setroundmode(CPUAlphaState *env, uint32_t val)
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{
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set_float_rounding_mode(val, &FP_STATUS);
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}
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void helper_setflushzero(CPUAlphaState *env, uint32_t val)
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{
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set_flush_to_zero(val, &FP_STATUS);
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}
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#define CONVERT_BIT(X, SRC, DST) \
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(SRC > DST ? (X) / (SRC / DST) & (DST) : ((X) & SRC) * (DST / SRC))
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static uint32_t soft_to_fpcr_exc(CPUAlphaState *env)
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{
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uint8_t exc = get_float_exception_flags(&FP_STATUS);
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uint32_t ret = 0;
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if (unlikely(exc)) {
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set_float_exception_flags(0, &FP_STATUS);
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ret |= CONVERT_BIT(exc, float_flag_invalid, FPCR_INV);
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ret |= CONVERT_BIT(exc, float_flag_divbyzero, FPCR_DZE);
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ret |= CONVERT_BIT(exc, float_flag_overflow, FPCR_OVF);
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ret |= CONVERT_BIT(exc, float_flag_underflow, FPCR_UNF);
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ret |= CONVERT_BIT(exc, float_flag_inexact, FPCR_INE);
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}
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return ret;
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}
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static void fp_exc_raise1(CPUAlphaState *env, uintptr_t retaddr,
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uint32_t exc, uint32_t regno, uint32_t hw_exc)
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{
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hw_exc |= CONVERT_BIT(exc, FPCR_INV, EXC_M_INV);
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hw_exc |= CONVERT_BIT(exc, FPCR_DZE, EXC_M_DZE);
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hw_exc |= CONVERT_BIT(exc, FPCR_OVF, EXC_M_FOV);
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hw_exc |= CONVERT_BIT(exc, FPCR_UNF, EXC_M_UNF);
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hw_exc |= CONVERT_BIT(exc, FPCR_INE, EXC_M_INE);
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hw_exc |= CONVERT_BIT(exc, FPCR_IOV, EXC_M_IOV);
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arith_excp(env, retaddr, hw_exc, 1ull << regno);
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}
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/* Raise exceptions for ieee fp insns without software completion.
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In that case there are no exceptions that don't trap; the mask
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doesn't apply. */
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void helper_fp_exc_raise(CPUAlphaState *env, uint32_t ignore, uint32_t regno)
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{
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uint32_t exc = env->error_code;
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if (exc) {
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env->fpcr |= exc;
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exc &= ~ignore;
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if (exc) {
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fp_exc_raise1(env, GETPC(), exc, regno, 0);
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}
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}
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}
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/* Raise exceptions for ieee fp insns with software completion. */
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void helper_fp_exc_raise_s(CPUAlphaState *env, uint32_t ignore, uint32_t regno)
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{
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uint32_t exc = env->error_code & ~ignore;
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if (exc) {
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env->fpcr |= exc;
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exc &= ~ignore;
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#ifdef CONFIG_USER_ONLY
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/*
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* In user mode, the kernel's software handler only
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* delivers a signal if the exception is enabled.
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*/
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if (!(exc & env->fpcr_exc_enable)) {
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return;
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}
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#else
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/*
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* In system mode, the software handler gets invoked
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* for any non-ignored exception.
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*/
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if (!exc) {
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return;
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}
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#endif
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exc &= env->fpcr_exc_enable;
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fp_exc_raise1(env, GETPC(), exc, regno, EXC_M_SWC);
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}
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}
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/* Input handing without software completion. Trap for all
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non-finite numbers. */
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void helper_ieee_input(CPUAlphaState *env, uint64_t val)
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{
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uint32_t exp = (uint32_t)(val >> 52) & 0x7ff;
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uint64_t frac = val & 0xfffffffffffffull;
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if (exp == 0) {
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/* Denormals without /S raise an exception. */
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if (frac != 0) {
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arith_excp(env, GETPC(), EXC_M_INV, 0);
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}
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} else if (exp == 0x7ff) {
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/* Infinity or NaN. */
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env->fpcr |= FPCR_INV;
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arith_excp(env, GETPC(), EXC_M_INV, 0);
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}
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}
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/* Similar, but does not trap for infinities. Used for comparisons. */
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void helper_ieee_input_cmp(CPUAlphaState *env, uint64_t val)
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{
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uint32_t exp = (uint32_t)(val >> 52) & 0x7ff;
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uint64_t frac = val & 0xfffffffffffffull;
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if (exp == 0) {
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/* Denormals without /S raise an exception. */
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if (frac != 0) {
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arith_excp(env, GETPC(), EXC_M_INV, 0);
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}
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} else if (exp == 0x7ff && frac) {
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/* NaN. */
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env->fpcr |= FPCR_INV;
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arith_excp(env, GETPC(), EXC_M_INV, 0);
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}
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}
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/* Input handing with software completion. Trap for denorms, unless DNZ
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is set. If we try to support DNOD (which none of the produced hardware
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did, AFAICS), we'll need to suppress the trap when FPCR.DNOD is set;
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then the code downstream of that will need to cope with denorms sans
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flush_input_to_zero. Most of it should work sanely, but there's
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nothing to compare with. */
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void helper_ieee_input_s(CPUAlphaState *env, uint64_t val)
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{
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if (unlikely(2 * val - 1 < 0x1fffffffffffffull)
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&& !env->fp_status.flush_inputs_to_zero) {
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arith_excp(env, GETPC(), EXC_M_INV | EXC_M_SWC, 0);
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}
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}
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/* S floating (single) */
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/* Taken from linux/arch/alpha/kernel/traps.c, s_mem_to_reg. */
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static inline uint64_t float32_to_s_int(uint32_t fi)
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{
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uint32_t frac = fi & 0x7fffff;
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uint32_t sign = fi >> 31;
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uint32_t exp_msb = (fi >> 30) & 1;
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uint32_t exp_low = (fi >> 23) & 0x7f;
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uint32_t exp;
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exp = (exp_msb << 10) | exp_low;
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if (exp_msb) {
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if (exp_low == 0x7f) {
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exp = 0x7ff;
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}
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} else {
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if (exp_low != 0x00) {
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exp |= 0x380;
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}
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}
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return (((uint64_t)sign << 63)
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| ((uint64_t)exp << 52)
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| ((uint64_t)frac << 29));
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}
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static inline uint64_t float32_to_s(float32 fa)
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{
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CPU_FloatU a;
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a.f = fa;
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return float32_to_s_int(a.l);
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}
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static inline uint32_t s_to_float32_int(uint64_t a)
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{
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return ((a >> 32) & 0xc0000000) | ((a >> 29) & 0x3fffffff);
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}
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static inline float32 s_to_float32(uint64_t a)
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{
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CPU_FloatU r;
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r.l = s_to_float32_int(a);
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return r.f;
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}
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uint32_t helper_s_to_memory(uint64_t a)
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{
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return s_to_float32_int(a);
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}
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uint64_t helper_memory_to_s(uint32_t a)
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{
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return float32_to_s_int(a);
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}
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uint64_t helper_adds(CPUAlphaState *env, uint64_t a, uint64_t b)
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{
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float32 fa, fb, fr;
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fa = s_to_float32(a);
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fb = s_to_float32(b);
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fr = float32_add(fa, fb, &FP_STATUS);
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env->error_code = soft_to_fpcr_exc(env);
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return float32_to_s(fr);
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}
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uint64_t helper_subs(CPUAlphaState *env, uint64_t a, uint64_t b)
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{
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float32 fa, fb, fr;
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fa = s_to_float32(a);
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fb = s_to_float32(b);
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fr = float32_sub(fa, fb, &FP_STATUS);
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env->error_code = soft_to_fpcr_exc(env);
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return float32_to_s(fr);
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}
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uint64_t helper_muls(CPUAlphaState *env, uint64_t a, uint64_t b)
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{
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float32 fa, fb, fr;
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fa = s_to_float32(a);
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fb = s_to_float32(b);
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fr = float32_mul(fa, fb, &FP_STATUS);
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env->error_code = soft_to_fpcr_exc(env);
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return float32_to_s(fr);
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}
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uint64_t helper_divs(CPUAlphaState *env, uint64_t a, uint64_t b)
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{
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float32 fa, fb, fr;
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fa = s_to_float32(a);
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fb = s_to_float32(b);
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fr = float32_div(fa, fb, &FP_STATUS);
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env->error_code = soft_to_fpcr_exc(env);
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return float32_to_s(fr);
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}
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uint64_t helper_sqrts(CPUAlphaState *env, uint64_t a)
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{
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float32 fa, fr;
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fa = s_to_float32(a);
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fr = float32_sqrt(fa, &FP_STATUS);
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env->error_code = soft_to_fpcr_exc(env);
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return float32_to_s(fr);
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}
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/* T floating (double) */
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static inline float64 t_to_float64(uint64_t a)
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{
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/* Memory format is the same as float64 */
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CPU_DoubleU r;
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r.ll = a;
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return r.d;
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}
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static inline uint64_t float64_to_t(float64 fa)
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{
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/* Memory format is the same as float64 */
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CPU_DoubleU r;
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r.d = fa;
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return r.ll;
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}
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uint64_t helper_addt(CPUAlphaState *env, uint64_t a, uint64_t b)
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{
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float64 fa, fb, fr;
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fa = t_to_float64(a);
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fb = t_to_float64(b);
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fr = float64_add(fa, fb, &FP_STATUS);
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env->error_code = soft_to_fpcr_exc(env);
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return float64_to_t(fr);
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}
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uint64_t helper_subt(CPUAlphaState *env, uint64_t a, uint64_t b)
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{
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float64 fa, fb, fr;
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fa = t_to_float64(a);
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fb = t_to_float64(b);
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fr = float64_sub(fa, fb, &FP_STATUS);
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env->error_code = soft_to_fpcr_exc(env);
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return float64_to_t(fr);
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}
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uint64_t helper_mult(CPUAlphaState *env, uint64_t a, uint64_t b)
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{
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float64 fa, fb, fr;
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fa = t_to_float64(a);
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fb = t_to_float64(b);
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fr = float64_mul(fa, fb, &FP_STATUS);
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env->error_code = soft_to_fpcr_exc(env);
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return float64_to_t(fr);
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}
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uint64_t helper_divt(CPUAlphaState *env, uint64_t a, uint64_t b)
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{
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float64 fa, fb, fr;
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fa = t_to_float64(a);
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fb = t_to_float64(b);
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fr = float64_div(fa, fb, &FP_STATUS);
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env->error_code = soft_to_fpcr_exc(env);
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return float64_to_t(fr);
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}
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uint64_t helper_sqrtt(CPUAlphaState *env, uint64_t a)
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{
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float64 fa, fr;
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fa = t_to_float64(a);
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fr = float64_sqrt(fa, &FP_STATUS);
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env->error_code = soft_to_fpcr_exc(env);
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return float64_to_t(fr);
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}
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/* Comparisons */
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uint64_t helper_cmptun(CPUAlphaState *env, uint64_t a, uint64_t b)
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{
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float64 fa, fb;
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uint64_t ret = 0;
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fa = t_to_float64(a);
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fb = t_to_float64(b);
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if (float64_unordered_quiet(fa, fb, &FP_STATUS)) {
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ret = 0x4000000000000000ULL;
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}
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env->error_code = soft_to_fpcr_exc(env);
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return ret;
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}
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uint64_t helper_cmpteq(CPUAlphaState *env, uint64_t a, uint64_t b)
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{
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float64 fa, fb;
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uint64_t ret = 0;
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fa = t_to_float64(a);
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fb = t_to_float64(b);
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if (float64_eq_quiet(fa, fb, &FP_STATUS)) {
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ret = 0x4000000000000000ULL;
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}
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env->error_code = soft_to_fpcr_exc(env);
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return ret;
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}
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uint64_t helper_cmptle(CPUAlphaState *env, uint64_t a, uint64_t b)
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{
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float64 fa, fb;
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uint64_t ret = 0;
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fa = t_to_float64(a);
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fb = t_to_float64(b);
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if (float64_le(fa, fb, &FP_STATUS)) {
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ret = 0x4000000000000000ULL;
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}
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env->error_code = soft_to_fpcr_exc(env);
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return ret;
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}
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|
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uint64_t helper_cmptlt(CPUAlphaState *env, uint64_t a, uint64_t b)
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{
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float64 fa, fb;
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uint64_t ret = 0;
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|
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fa = t_to_float64(a);
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fb = t_to_float64(b);
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|
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if (float64_lt(fa, fb, &FP_STATUS)) {
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ret = 0x4000000000000000ULL;
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}
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env->error_code = soft_to_fpcr_exc(env);
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|
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return ret;
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}
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|
|
/* Floating point format conversion */
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uint64_t helper_cvtts(CPUAlphaState *env, uint64_t a)
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{
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float64 fa;
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float32 fr;
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|
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fa = t_to_float64(a);
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fr = float64_to_float32(fa, &FP_STATUS);
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env->error_code = soft_to_fpcr_exc(env);
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|
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return float32_to_s(fr);
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}
|
|
|
|
uint64_t helper_cvtst(CPUAlphaState *env, uint64_t a)
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{
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float32 fa;
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float64 fr;
|
|
|
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fa = s_to_float32(a);
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fr = float32_to_float64(fa, &FP_STATUS);
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env->error_code = soft_to_fpcr_exc(env);
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|
|
return float64_to_t(fr);
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}
|
|
|
|
uint64_t helper_cvtqs(CPUAlphaState *env, uint64_t a)
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|
{
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float32 fr = int64_to_float32(a, &FP_STATUS);
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env->error_code = soft_to_fpcr_exc(env);
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|
|
return float32_to_s(fr);
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}
|
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|
|
/* Implement float64 to uint64_t conversion without saturation -- we must
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|
supply the truncated result. This behaviour is used by the compiler
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|
to get unsigned conversion for free with the same instruction. */
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|
|
|
static uint64_t do_cvttq(CPUAlphaState *env, uint64_t a, int roundmode)
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|
{
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uint64_t frac, ret = 0;
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uint32_t exp, sign, exc = 0;
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int shift;
|
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sign = (a >> 63);
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exp = (uint32_t)(a >> 52) & 0x7ff;
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frac = a & 0xfffffffffffffull;
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|
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if (exp == 0) {
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if (unlikely(frac != 0) && !env->fp_status.flush_inputs_to_zero) {
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goto do_underflow;
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}
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} else if (exp == 0x7ff) {
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exc = FPCR_INV;
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} else {
|
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/* Restore implicit bit. */
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frac |= 0x10000000000000ull;
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shift = exp - 1023 - 52;
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if (shift >= 0) {
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/* In this case the number is so large that we must shift
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the fraction left. There is no rounding to do. */
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if (shift < 64) {
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ret = frac << shift;
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}
|
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/* Check for overflow. Note the special case of -0x1p63. */
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if (shift >= 11 && a != 0xC3E0000000000000ull) {
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exc = FPCR_IOV | FPCR_INE;
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}
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} else {
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uint64_t round;
|
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|
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/* In this case the number is smaller than the fraction as
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represented by the 52 bit number. Here we must think
|
|
about rounding the result. Handle this by shifting the
|
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fractional part of the number into the high bits of ROUND.
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|
This will let us efficiently handle round-to-nearest. */
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shift = -shift;
|
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if (shift < 63) {
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ret = frac >> shift;
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round = frac << (64 - shift);
|
|
} else {
|
|
/* The exponent is so small we shift out everything.
|
|
Leave a sticky bit for proper rounding below. */
|
|
do_underflow:
|
|
round = 1;
|
|
}
|
|
|
|
if (round) {
|
|
exc = FPCR_INE;
|
|
switch (roundmode) {
|
|
case float_round_nearest_even:
|
|
if (round == (1ull << 63)) {
|
|
/* Fraction is exactly 0.5; round to even. */
|
|
ret += (ret & 1);
|
|
} else if (round > (1ull << 63)) {
|
|
ret += 1;
|
|
}
|
|
break;
|
|
case float_round_to_zero:
|
|
break;
|
|
case float_round_up:
|
|
ret += 1 - sign;
|
|
break;
|
|
case float_round_down:
|
|
ret += sign;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
if (sign) {
|
|
ret = -ret;
|
|
}
|
|
}
|
|
env->error_code = exc;
|
|
|
|
return ret;
|
|
}
|
|
|
|
uint64_t helper_cvttq(CPUAlphaState *env, uint64_t a)
|
|
{
|
|
return do_cvttq(env, a, FP_STATUS.float_rounding_mode);
|
|
}
|
|
|
|
uint64_t helper_cvttq_c(CPUAlphaState *env, uint64_t a)
|
|
{
|
|
return do_cvttq(env, a, float_round_to_zero);
|
|
}
|
|
|
|
uint64_t helper_cvtqt(CPUAlphaState *env, uint64_t a)
|
|
{
|
|
float64 fr = int64_to_float64(a, &FP_STATUS);
|
|
env->error_code = soft_to_fpcr_exc(env);
|
|
return float64_to_t(fr);
|
|
}
|
|
|
|
uint64_t helper_cvtql(CPUAlphaState *env, uint64_t val)
|
|
{
|
|
uint32_t exc = 0;
|
|
if (val != (int32_t)val) {
|
|
exc = FPCR_IOV | FPCR_INE;
|
|
}
|
|
env->error_code = exc;
|
|
|
|
return ((val & 0xc0000000) << 32) | ((val & 0x3fffffff) << 29);
|
|
}
|