ShihPo Hung 613fa160e1 target/riscv: Fix tb->flags FS status ... It was found that running libquantum on riscv-linux qemu produced an incorrect result. After investigation, FP registers are not saved during context switch due to incorrect mstatus.FS. In current implementation tb->flags merges all non-disabled state to dirty. This means the code in mark_fs_dirty in translate.c that handles initial and clean states is unreachable. This patch fixes it and is successfully tested with: libquantum Thanks to Richard for pointing out the actual bug. v3: remove the redundant condition v2: root cause FS problem Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: ShihPo Hung <shihpo.hung@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>		2020-01-16 10:02:58 -08:00
..
insn_trans	tcg: TCGMemOp is now accelerator independent MemOp	2019-09-03 08:30:38 -07:00
cpu-param.h	tcg: Split out target/arch/cpu-param.h	2019-06-10 07:03:34 -07:00
cpu.c	target/riscv: Remove atomic accesses to MIP CSR	2019-11-14 09:53:28 -08:00
cpu.h	target/riscv: Fix tb->flags FS status	2020-01-16 10:02:58 -08:00
cpu_bits.h	target/riscv: Update the Hypervisor CSRs to v0.4	2019-09-17 08:42:43 -07:00
cpu_helper.c	target/riscv: Remove atomic accesses to MIP CSR	2019-11-14 09:53:28 -08:00
cpu_user.h	Supply missing header guards	2019-06-12 13:20:21 +02:00
csr.c	target/riscv: Remove atomic accesses to MIP CSR	2019-11-14 09:53:28 -08:00
fpu_helper.c	target/riscv: rationalise softfloat includes	2019-08-19 12:07:13 +01:00
gdbstub.c	target/riscv: Make the priv register writable by GDB	2019-10-28 07:47:29 -07:00
helper.h	RISC-V CPU Helpers	2018-03-07 08:30:28 +13:00
insn16-32.decode	target/riscv: Split RVC32 and RVC64 insns into separate files	2019-05-24 12:09:22 -07:00
insn16-64.decode	target/riscv: Add checks for several RVC reserved operands	2019-05-24 12:09:25 -07:00
insn16.decode	target/riscv: Add checks for several RVC reserved operands	2019-05-24 12:09:25 -07:00
insn32-64.decode	target/riscv: Convert RV64D insns to decodetree	2019-03-13 10:34:06 +01:00
insn32.decode	target/riscv: Name the argument sets for all of insn32 formats	2019-05-24 12:09:22 -07:00
instmap.h	Supply missing header guards	2019-06-12 13:20:21 +02:00
Makefile.objs	riscv: hmp: Add a command to show virtual memory mappings	2019-09-17 08:42:43 -07:00
monitor.c	riscv: hmp: Add a command to show virtual memory mappings	2019-09-17 08:42:43 -07:00
op_helper.c	riscv: Set xPIE to 1 after xRET	2020-01-16 10:02:41 -08:00
pmp.c	target/riscv: PMP violation due to wrong size parameter	2019-10-28 08:46:33 -07:00
pmp.h	RISC-V: Check for the effective memory privilege mode during PMP checks	2019-06-23 23:44:41 -07:00
trace-events	target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events	2019-09-17 08:42:42 -07:00
translate.c	remove unnecessary ifdef TARGET_RISCV64	2019-11-14 09:53:28 -08:00