Previous work on dev-iotlb message broke spapr_iommu/vhost integration as it did for SMMU and virtio-iommu. The spapr_iommu currently only sends IOMMU_NOTIFIER_UNMAP notifications. Since commit958ec334bc
("vhost: Unbreak SMMU and virtio-iommu on dev-iotlb support"), VHOST first tries to register IOMMU_NOTIFIER_DEVIOTLB_UNMAP notifier and if it fails, falls back to legacy IOMMU_NOTIFIER_UNMAP. So spapr_iommu must fail on the IOMMU_NOTIFIER_DEVIOTLB_UNMAP registration. Reported-by: Peter Xu <peterx@redhat.com> Fixes:b68ba1ca57
("memory: Add IOMMU_NOTIFIER_DEVIOTLB_UNMAP IOMMUTLBNotificationType") Signed-off-by: Eric Auger <eric.auger@redhat.com> Message-Id: <20210209213233.40985-3-eric.auger@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Acked-by: Jason Wang <jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
720 lines
20 KiB
C
720 lines
20 KiB
C
/*
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* QEMU sPAPR IOMMU (TCE) code
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*
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* Copyright (c) 2010 David Gibson, IBM Corporation <dwg@au1.ibm.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/error-report.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "sysemu/kvm.h"
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#include "kvm_ppc.h"
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#include "migration/vmstate.h"
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#include "sysemu/dma.h"
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#include "exec/address-spaces.h"
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#include "trace.h"
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#include "hw/ppc/spapr.h"
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#include "hw/ppc/spapr_vio.h"
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#include <libfdt.h>
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enum SpaprTceAccess {
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SPAPR_TCE_FAULT = 0,
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SPAPR_TCE_RO = 1,
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SPAPR_TCE_WO = 2,
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SPAPR_TCE_RW = 3,
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};
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#define IOMMU_PAGE_SIZE(shift) (1ULL << (shift))
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#define IOMMU_PAGE_MASK(shift) (~(IOMMU_PAGE_SIZE(shift) - 1))
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static QLIST_HEAD(, SpaprTceTable) spapr_tce_tables;
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SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn)
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{
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SpaprTceTable *tcet;
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if (liobn & 0xFFFFFFFF00000000ULL) {
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hcall_dprintf("Request for out-of-bounds LIOBN 0x" TARGET_FMT_lx "\n",
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liobn);
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return NULL;
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}
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QLIST_FOREACH(tcet, &spapr_tce_tables, list) {
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if (tcet->liobn == (uint32_t)liobn) {
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return tcet;
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}
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}
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return NULL;
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}
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static IOMMUAccessFlags spapr_tce_iommu_access_flags(uint64_t tce)
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{
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switch (tce & SPAPR_TCE_RW) {
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case SPAPR_TCE_FAULT:
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return IOMMU_NONE;
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case SPAPR_TCE_RO:
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return IOMMU_RO;
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case SPAPR_TCE_WO:
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return IOMMU_WO;
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default: /* SPAPR_TCE_RW */
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return IOMMU_RW;
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}
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}
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static uint64_t *spapr_tce_alloc_table(uint32_t liobn,
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uint32_t page_shift,
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uint64_t bus_offset,
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uint32_t nb_table,
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int *fd,
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bool need_vfio)
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{
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uint64_t *table = NULL;
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if (kvm_enabled()) {
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table = kvmppc_create_spapr_tce(liobn, page_shift, bus_offset, nb_table,
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fd, need_vfio);
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}
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if (!table) {
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*fd = -1;
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table = g_new0(uint64_t, nb_table);
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}
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trace_spapr_iommu_new_table(liobn, table, *fd);
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return table;
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}
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static void spapr_tce_free_table(uint64_t *table, int fd, uint32_t nb_table)
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{
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if (!kvm_enabled() ||
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(kvmppc_remove_spapr_tce(table, fd, nb_table) != 0)) {
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g_free(table);
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}
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}
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/* Called from RCU critical section */
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static IOMMUTLBEntry spapr_tce_translate_iommu(IOMMUMemoryRegion *iommu,
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hwaddr addr,
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IOMMUAccessFlags flag,
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int iommu_idx)
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{
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SpaprTceTable *tcet = container_of(iommu, SpaprTceTable, iommu);
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uint64_t tce;
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IOMMUTLBEntry ret = {
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.target_as = &address_space_memory,
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.iova = 0,
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.translated_addr = 0,
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.addr_mask = ~(hwaddr)0,
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.perm = IOMMU_NONE,
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};
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if ((addr >> tcet->page_shift) < tcet->nb_table) {
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/* Check if we are in bound */
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hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
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tce = tcet->table[addr >> tcet->page_shift];
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ret.iova = addr & page_mask;
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ret.translated_addr = tce & page_mask;
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ret.addr_mask = ~page_mask;
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ret.perm = spapr_tce_iommu_access_flags(tce);
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}
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trace_spapr_iommu_xlate(tcet->liobn, addr, ret.translated_addr, ret.perm,
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ret.addr_mask);
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return ret;
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}
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static void spapr_tce_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
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{
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MemoryRegion *mr = MEMORY_REGION(iommu_mr);
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IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
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hwaddr addr, granularity;
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IOMMUTLBEntry iotlb;
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SpaprTceTable *tcet = container_of(iommu_mr, SpaprTceTable, iommu);
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if (tcet->skipping_replay) {
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return;
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}
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granularity = memory_region_iommu_get_min_page_size(iommu_mr);
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for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
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iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, n->iommu_idx);
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if (iotlb.perm != IOMMU_NONE) {
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n->notify(n, &iotlb);
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}
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/*
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* if (2^64 - MR size) < granularity, it's possible to get an
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* infinite loop here. This should catch such a wraparound.
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*/
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if ((addr + granularity) < addr) {
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break;
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}
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}
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}
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static int spapr_tce_table_pre_save(void *opaque)
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{
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SpaprTceTable *tcet = SPAPR_TCE_TABLE(opaque);
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tcet->mig_table = tcet->table;
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tcet->mig_nb_table = tcet->nb_table;
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trace_spapr_iommu_pre_save(tcet->liobn, tcet->mig_nb_table,
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tcet->bus_offset, tcet->page_shift);
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return 0;
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}
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static uint64_t spapr_tce_get_min_page_size(IOMMUMemoryRegion *iommu)
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{
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SpaprTceTable *tcet = container_of(iommu, SpaprTceTable, iommu);
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return 1ULL << tcet->page_shift;
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}
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static int spapr_tce_get_attr(IOMMUMemoryRegion *iommu,
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enum IOMMUMemoryRegionAttr attr, void *data)
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{
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SpaprTceTable *tcet = container_of(iommu, SpaprTceTable, iommu);
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if (attr == IOMMU_ATTR_SPAPR_TCE_FD && kvmppc_has_cap_spapr_vfio()) {
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*(int *) data = tcet->fd;
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return 0;
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}
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return -EINVAL;
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}
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static int spapr_tce_notify_flag_changed(IOMMUMemoryRegion *iommu,
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IOMMUNotifierFlag old,
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IOMMUNotifierFlag new,
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Error **errp)
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{
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struct SpaprTceTable *tbl = container_of(iommu, SpaprTceTable, iommu);
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if (new & IOMMU_NOTIFIER_DEVIOTLB_UNMAP) {
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error_setg(errp, "spart_tce does not support dev-iotlb yet");
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return -EINVAL;
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}
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if (old == IOMMU_NOTIFIER_NONE && new != IOMMU_NOTIFIER_NONE) {
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spapr_tce_set_need_vfio(tbl, true);
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} else if (old != IOMMU_NOTIFIER_NONE && new == IOMMU_NOTIFIER_NONE) {
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spapr_tce_set_need_vfio(tbl, false);
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}
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return 0;
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}
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static int spapr_tce_table_post_load(void *opaque, int version_id)
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{
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SpaprTceTable *tcet = SPAPR_TCE_TABLE(opaque);
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uint32_t old_nb_table = tcet->nb_table;
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uint64_t old_bus_offset = tcet->bus_offset;
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uint32_t old_page_shift = tcet->page_shift;
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if (tcet->vdev) {
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spapr_vio_set_bypass(tcet->vdev, tcet->bypass);
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}
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if (tcet->mig_nb_table != tcet->nb_table) {
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spapr_tce_table_disable(tcet);
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}
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if (tcet->mig_nb_table) {
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if (!tcet->nb_table) {
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spapr_tce_table_enable(tcet, old_page_shift, old_bus_offset,
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tcet->mig_nb_table);
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}
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memcpy(tcet->table, tcet->mig_table,
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tcet->nb_table * sizeof(tcet->table[0]));
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free(tcet->mig_table);
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tcet->mig_table = NULL;
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}
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trace_spapr_iommu_post_load(tcet->liobn, old_nb_table, tcet->nb_table,
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tcet->bus_offset, tcet->page_shift);
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return 0;
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}
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static bool spapr_tce_table_ex_needed(void *opaque)
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{
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SpaprTceTable *tcet = opaque;
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return tcet->bus_offset || tcet->page_shift != 0xC;
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}
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static const VMStateDescription vmstate_spapr_tce_table_ex = {
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.name = "spapr_iommu_ex",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = spapr_tce_table_ex_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(bus_offset, SpaprTceTable),
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VMSTATE_UINT32(page_shift, SpaprTceTable),
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VMSTATE_END_OF_LIST()
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},
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};
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static const VMStateDescription vmstate_spapr_tce_table = {
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.name = "spapr_iommu",
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.version_id = 2,
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.minimum_version_id = 2,
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.pre_save = spapr_tce_table_pre_save,
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.post_load = spapr_tce_table_post_load,
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.fields = (VMStateField []) {
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/* Sanity check */
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VMSTATE_UINT32_EQUAL(liobn, SpaprTceTable, NULL),
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/* IOMMU state */
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VMSTATE_UINT32(mig_nb_table, SpaprTceTable),
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VMSTATE_BOOL(bypass, SpaprTceTable),
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VMSTATE_VARRAY_UINT32_ALLOC(mig_table, SpaprTceTable, mig_nb_table, 0,
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vmstate_info_uint64, uint64_t),
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VMSTATE_END_OF_LIST()
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},
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.subsections = (const VMStateDescription*[]) {
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&vmstate_spapr_tce_table_ex,
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NULL
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}
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};
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static void spapr_tce_table_realize(DeviceState *dev, Error **errp)
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{
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SpaprTceTable *tcet = SPAPR_TCE_TABLE(dev);
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Object *tcetobj = OBJECT(tcet);
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gchar *tmp;
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tcet->fd = -1;
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tcet->need_vfio = false;
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tmp = g_strdup_printf("tce-root-%x", tcet->liobn);
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memory_region_init(&tcet->root, tcetobj, tmp, UINT64_MAX);
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g_free(tmp);
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tmp = g_strdup_printf("tce-iommu-%x", tcet->liobn);
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memory_region_init_iommu(&tcet->iommu, sizeof(tcet->iommu),
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TYPE_SPAPR_IOMMU_MEMORY_REGION,
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tcetobj, tmp, 0);
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g_free(tmp);
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QLIST_INSERT_HEAD(&spapr_tce_tables, tcet, list);
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vmstate_register(VMSTATE_IF(tcet), tcet->liobn, &vmstate_spapr_tce_table,
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tcet);
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}
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void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio)
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{
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size_t table_size = tcet->nb_table * sizeof(uint64_t);
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uint64_t *oldtable;
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int newfd = -1;
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g_assert(need_vfio != tcet->need_vfio);
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tcet->need_vfio = need_vfio;
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if (!need_vfio || (tcet->fd != -1 && kvmppc_has_cap_spapr_vfio())) {
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return;
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}
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oldtable = tcet->table;
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tcet->table = spapr_tce_alloc_table(tcet->liobn,
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tcet->page_shift,
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tcet->bus_offset,
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tcet->nb_table,
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&newfd,
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need_vfio);
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memcpy(tcet->table, oldtable, table_size);
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spapr_tce_free_table(oldtable, tcet->fd, tcet->nb_table);
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tcet->fd = newfd;
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}
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SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn)
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{
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SpaprTceTable *tcet;
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gchar *tmp;
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if (spapr_tce_find_by_liobn(liobn)) {
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error_report("Attempted to create TCE table with duplicate"
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" LIOBN 0x%x", liobn);
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return NULL;
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}
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tcet = SPAPR_TCE_TABLE(object_new(TYPE_SPAPR_TCE_TABLE));
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tcet->liobn = liobn;
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tmp = g_strdup_printf("tce-table-%x", liobn);
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object_property_add_child(OBJECT(owner), tmp, OBJECT(tcet));
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g_free(tmp);
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object_unref(OBJECT(tcet));
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qdev_realize(DEVICE(tcet), NULL, NULL);
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return tcet;
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}
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void spapr_tce_table_enable(SpaprTceTable *tcet,
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uint32_t page_shift, uint64_t bus_offset,
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uint32_t nb_table)
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{
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if (tcet->nb_table) {
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warn_report("trying to enable already enabled TCE table");
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return;
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}
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tcet->bus_offset = bus_offset;
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tcet->page_shift = page_shift;
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tcet->nb_table = nb_table;
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tcet->table = spapr_tce_alloc_table(tcet->liobn,
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tcet->page_shift,
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tcet->bus_offset,
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tcet->nb_table,
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&tcet->fd,
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tcet->need_vfio);
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memory_region_set_size(MEMORY_REGION(&tcet->iommu),
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(uint64_t)tcet->nb_table << tcet->page_shift);
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memory_region_add_subregion(&tcet->root, tcet->bus_offset,
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MEMORY_REGION(&tcet->iommu));
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}
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void spapr_tce_table_disable(SpaprTceTable *tcet)
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{
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if (!tcet->nb_table) {
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return;
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}
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memory_region_del_subregion(&tcet->root, MEMORY_REGION(&tcet->iommu));
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memory_region_set_size(MEMORY_REGION(&tcet->iommu), 0);
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spapr_tce_free_table(tcet->table, tcet->fd, tcet->nb_table);
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tcet->fd = -1;
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tcet->table = NULL;
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tcet->bus_offset = 0;
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tcet->page_shift = 0;
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tcet->nb_table = 0;
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}
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static void spapr_tce_table_unrealize(DeviceState *dev)
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{
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SpaprTceTable *tcet = SPAPR_TCE_TABLE(dev);
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vmstate_unregister(VMSTATE_IF(tcet), &vmstate_spapr_tce_table, tcet);
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QLIST_REMOVE(tcet, list);
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spapr_tce_table_disable(tcet);
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}
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MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet)
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{
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return &tcet->root;
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}
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static void spapr_tce_reset(DeviceState *dev)
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{
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SpaprTceTable *tcet = SPAPR_TCE_TABLE(dev);
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size_t table_size = tcet->nb_table * sizeof(uint64_t);
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if (tcet->nb_table) {
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memset(tcet->table, 0, table_size);
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}
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}
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static target_ulong put_tce_emu(SpaprTceTable *tcet, target_ulong ioba,
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target_ulong tce)
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{
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IOMMUTLBEvent event;
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hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
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unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift;
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if (index >= tcet->nb_table) {
|
|
hcall_dprintf("spapr_vio_put_tce on out-of-bounds IOBA 0x"
|
|
TARGET_FMT_lx "\n", ioba);
|
|
return H_PARAMETER;
|
|
}
|
|
|
|
tcet->table[index] = tce;
|
|
|
|
event.entry.target_as = &address_space_memory,
|
|
event.entry.iova = (ioba - tcet->bus_offset) & page_mask;
|
|
event.entry.translated_addr = tce & page_mask;
|
|
event.entry.addr_mask = ~page_mask;
|
|
event.entry.perm = spapr_tce_iommu_access_flags(tce);
|
|
event.type = event.entry.perm ? IOMMU_NOTIFIER_MAP : IOMMU_NOTIFIER_UNMAP;
|
|
memory_region_notify_iommu(&tcet->iommu, 0, event);
|
|
|
|
return H_SUCCESS;
|
|
}
|
|
|
|
static target_ulong h_put_tce_indirect(PowerPCCPU *cpu,
|
|
SpaprMachineState *spapr,
|
|
target_ulong opcode, target_ulong *args)
|
|
{
|
|
int i;
|
|
target_ulong liobn = args[0];
|
|
target_ulong ioba = args[1];
|
|
target_ulong ioba1 = ioba;
|
|
target_ulong tce_list = args[2];
|
|
target_ulong npages = args[3];
|
|
target_ulong ret = H_PARAMETER, tce = 0;
|
|
SpaprTceTable *tcet = spapr_tce_find_by_liobn(liobn);
|
|
CPUState *cs = CPU(cpu);
|
|
hwaddr page_mask, page_size;
|
|
|
|
if (!tcet) {
|
|
return H_PARAMETER;
|
|
}
|
|
|
|
if ((npages > 512) || (tce_list & SPAPR_TCE_PAGE_MASK)) {
|
|
return H_PARAMETER;
|
|
}
|
|
|
|
page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
|
|
page_size = IOMMU_PAGE_SIZE(tcet->page_shift);
|
|
ioba &= page_mask;
|
|
|
|
for (i = 0; i < npages; ++i, ioba += page_size) {
|
|
tce = ldq_be_phys(cs->as, tce_list + i * sizeof(target_ulong));
|
|
|
|
ret = put_tce_emu(tcet, ioba, tce);
|
|
if (ret) {
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Trace last successful or the first problematic entry */
|
|
i = i ? (i - 1) : 0;
|
|
if (SPAPR_IS_PCI_LIOBN(liobn)) {
|
|
trace_spapr_iommu_pci_indirect(liobn, ioba1, tce_list, i, tce, ret);
|
|
} else {
|
|
trace_spapr_iommu_indirect(liobn, ioba1, tce_list, i, tce, ret);
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static target_ulong h_stuff_tce(PowerPCCPU *cpu, SpaprMachineState *spapr,
|
|
target_ulong opcode, target_ulong *args)
|
|
{
|
|
int i;
|
|
target_ulong liobn = args[0];
|
|
target_ulong ioba = args[1];
|
|
target_ulong tce_value = args[2];
|
|
target_ulong npages = args[3];
|
|
target_ulong ret = H_PARAMETER;
|
|
SpaprTceTable *tcet = spapr_tce_find_by_liobn(liobn);
|
|
hwaddr page_mask, page_size;
|
|
|
|
if (!tcet) {
|
|
return H_PARAMETER;
|
|
}
|
|
|
|
if (npages > tcet->nb_table) {
|
|
return H_PARAMETER;
|
|
}
|
|
|
|
page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
|
|
page_size = IOMMU_PAGE_SIZE(tcet->page_shift);
|
|
ioba &= page_mask;
|
|
|
|
for (i = 0; i < npages; ++i, ioba += page_size) {
|
|
ret = put_tce_emu(tcet, ioba, tce_value);
|
|
if (ret) {
|
|
break;
|
|
}
|
|
}
|
|
if (SPAPR_IS_PCI_LIOBN(liobn)) {
|
|
trace_spapr_iommu_pci_stuff(liobn, ioba, tce_value, npages, ret);
|
|
} else {
|
|
trace_spapr_iommu_stuff(liobn, ioba, tce_value, npages, ret);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static target_ulong h_put_tce(PowerPCCPU *cpu, SpaprMachineState *spapr,
|
|
target_ulong opcode, target_ulong *args)
|
|
{
|
|
target_ulong liobn = args[0];
|
|
target_ulong ioba = args[1];
|
|
target_ulong tce = args[2];
|
|
target_ulong ret = H_PARAMETER;
|
|
SpaprTceTable *tcet = spapr_tce_find_by_liobn(liobn);
|
|
|
|
if (tcet) {
|
|
hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
|
|
|
|
ioba &= page_mask;
|
|
|
|
ret = put_tce_emu(tcet, ioba, tce);
|
|
}
|
|
if (SPAPR_IS_PCI_LIOBN(liobn)) {
|
|
trace_spapr_iommu_pci_put(liobn, ioba, tce, ret);
|
|
} else {
|
|
trace_spapr_iommu_put(liobn, ioba, tce, ret);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static target_ulong get_tce_emu(SpaprTceTable *tcet, target_ulong ioba,
|
|
target_ulong *tce)
|
|
{
|
|
unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift;
|
|
|
|
if (index >= tcet->nb_table) {
|
|
hcall_dprintf("spapr_iommu_get_tce on out-of-bounds IOBA 0x"
|
|
TARGET_FMT_lx "\n", ioba);
|
|
return H_PARAMETER;
|
|
}
|
|
|
|
*tce = tcet->table[index];
|
|
|
|
return H_SUCCESS;
|
|
}
|
|
|
|
static target_ulong h_get_tce(PowerPCCPU *cpu, SpaprMachineState *spapr,
|
|
target_ulong opcode, target_ulong *args)
|
|
{
|
|
target_ulong liobn = args[0];
|
|
target_ulong ioba = args[1];
|
|
target_ulong tce = 0;
|
|
target_ulong ret = H_PARAMETER;
|
|
SpaprTceTable *tcet = spapr_tce_find_by_liobn(liobn);
|
|
|
|
if (tcet) {
|
|
hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
|
|
|
|
ioba &= page_mask;
|
|
|
|
ret = get_tce_emu(tcet, ioba, &tce);
|
|
if (!ret) {
|
|
args[0] = tce;
|
|
}
|
|
}
|
|
if (SPAPR_IS_PCI_LIOBN(liobn)) {
|
|
trace_spapr_iommu_pci_get(liobn, ioba, ret, tce);
|
|
} else {
|
|
trace_spapr_iommu_get(liobn, ioba, ret, tce);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
int spapr_dma_dt(void *fdt, int node_off, const char *propname,
|
|
uint32_t liobn, uint64_t window, uint32_t size)
|
|
{
|
|
uint32_t dma_prop[5];
|
|
int ret;
|
|
|
|
dma_prop[0] = cpu_to_be32(liobn);
|
|
dma_prop[1] = cpu_to_be32(window >> 32);
|
|
dma_prop[2] = cpu_to_be32(window & 0xFFFFFFFF);
|
|
dma_prop[3] = 0; /* window size is 32 bits */
|
|
dma_prop[4] = cpu_to_be32(size);
|
|
|
|
ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-address-cells", 2);
|
|
if (ret < 0) {
|
|
return ret;
|
|
}
|
|
|
|
ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-size-cells", 2);
|
|
if (ret < 0) {
|
|
return ret;
|
|
}
|
|
|
|
ret = fdt_setprop(fdt, node_off, propname, dma_prop, sizeof(dma_prop));
|
|
if (ret < 0) {
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
|
|
SpaprTceTable *tcet)
|
|
{
|
|
if (!tcet) {
|
|
return 0;
|
|
}
|
|
|
|
return spapr_dma_dt(fdt, node_off, propname,
|
|
tcet->liobn, 0, tcet->nb_table << tcet->page_shift);
|
|
}
|
|
|
|
static void spapr_tce_table_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
dc->realize = spapr_tce_table_realize;
|
|
dc->reset = spapr_tce_reset;
|
|
dc->unrealize = spapr_tce_table_unrealize;
|
|
/* Reason: This is just an internal device for handling the hypercalls */
|
|
dc->user_creatable = false;
|
|
|
|
QLIST_INIT(&spapr_tce_tables);
|
|
|
|
/* hcall-tce */
|
|
spapr_register_hypercall(H_PUT_TCE, h_put_tce);
|
|
spapr_register_hypercall(H_GET_TCE, h_get_tce);
|
|
spapr_register_hypercall(H_PUT_TCE_INDIRECT, h_put_tce_indirect);
|
|
spapr_register_hypercall(H_STUFF_TCE, h_stuff_tce);
|
|
}
|
|
|
|
static TypeInfo spapr_tce_table_info = {
|
|
.name = TYPE_SPAPR_TCE_TABLE,
|
|
.parent = TYPE_DEVICE,
|
|
.instance_size = sizeof(SpaprTceTable),
|
|
.class_init = spapr_tce_table_class_init,
|
|
};
|
|
|
|
static void spapr_iommu_memory_region_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
|
|
|
|
imrc->translate = spapr_tce_translate_iommu;
|
|
imrc->replay = spapr_tce_replay;
|
|
imrc->get_min_page_size = spapr_tce_get_min_page_size;
|
|
imrc->notify_flag_changed = spapr_tce_notify_flag_changed;
|
|
imrc->get_attr = spapr_tce_get_attr;
|
|
}
|
|
|
|
static const TypeInfo spapr_iommu_memory_region_info = {
|
|
.parent = TYPE_IOMMU_MEMORY_REGION,
|
|
.name = TYPE_SPAPR_IOMMU_MEMORY_REGION,
|
|
.class_init = spapr_iommu_memory_region_class_init,
|
|
};
|
|
|
|
static void register_types(void)
|
|
{
|
|
type_register_static(&spapr_tce_table_info);
|
|
type_register_static(&spapr_iommu_memory_region_info);
|
|
}
|
|
|
|
type_init(register_types);
|