Michael Clark 65c5b75c38 RISC-V Physical Memory Protection ... Implements the physical memory protection extension as specified in Privileged ISA Version 1.10. PMP (Physical Memory Protection) is as-of-yet unused and needs testing. The SiFive verification team have PMP test cases that will be run. Nothing currently depends on PMP support. It would be preferable to keep the code in-tree for folk that are interested in RISC-V PMP support. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Daire McNamara <daire.mcnamara@emdalo.com> Signed-off-by: Ivan Griffin <ivan.griffin@emdalo.com> Signed-off-by: Michael Clark <mjc@sifive.com>		2018-03-07 08:30:28 +13:00
..
cpu.c
cpu.h
cpu_bits.h
fpu_helper.c	RISC-V FPU Support	2018-03-07 08:30:28 +13:00
gdbstub.c	RISC-V GDB Stub	2018-03-07 08:30:28 +13:00
helper.c	RISC-V CPU Helpers	2018-03-07 08:30:28 +13:00
helper.h	RISC-V CPU Helpers	2018-03-07 08:30:28 +13:00
instmap.h	RISC-V TCG Code Generation	2018-03-07 08:30:28 +13:00
op_helper.c	RISC-V CPU Helpers	2018-03-07 08:30:28 +13:00
pmp.c	RISC-V Physical Memory Protection	2018-03-07 08:30:28 +13:00
pmp.h	RISC-V Physical Memory Protection	2018-03-07 08:30:28 +13:00
translate.c	RISC-V TCG Code Generation	2018-03-07 08:30:28 +13:00