This patch introduces three memory-management-related functions that will become part of AVR CPU class object. [AM: Split a larger AVR introduction patch into logical units] Suggested-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com> Co-developed-by: Michael Rolnik <mrolnik@gmail.com> Co-developed-by: Sarah Harris <S.E.Harris@kent.ac.uk> Signed-off-by: Michael Rolnik <mrolnik@gmail.com> Signed-off-by: Sarah Harris <S.E.Harris@kent.ac.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com> Acked-by: Igor Mammedov <imammedo@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <huth@tuxfamily.org> Message-Id: <20200705140315.260514-5-huth@tuxfamily.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
140 lines
4.2 KiB
C
140 lines
4.2 KiB
C
/*
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* QEMU AVR CPU helpers
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*
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* Copyright (c) 2016-2020 Michael Rolnik
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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{
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bool ret = false;
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CPUClass *cc = CPU_GET_CLASS(cs);
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AVRCPU *cpu = AVR_CPU(cs);
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CPUAVRState *env = &cpu->env;
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if (interrupt_request & CPU_INTERRUPT_RESET) {
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if (cpu_interrupts_enabled(env)) {
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cs->exception_index = EXCP_RESET;
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cc->do_interrupt(cs);
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cs->interrupt_request &= ~CPU_INTERRUPT_RESET;
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ret = true;
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}
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}
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if (interrupt_request & CPU_INTERRUPT_HARD) {
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if (cpu_interrupts_enabled(env) && env->intsrc != 0) {
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int index = ctz32(env->intsrc);
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cs->exception_index = EXCP_INT(index);
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cc->do_interrupt(cs);
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env->intsrc &= env->intsrc - 1; /* clear the interrupt */
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cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
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ret = true;
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}
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}
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return ret;
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}
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void avr_cpu_do_interrupt(CPUState *cs)
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{
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AVRCPU *cpu = AVR_CPU(cs);
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CPUAVRState *env = &cpu->env;
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uint32_t ret = env->pc_w;
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int vector = 0;
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int size = avr_feature(env, AVR_FEATURE_JMP_CALL) ? 2 : 1;
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int base = 0;
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if (cs->exception_index == EXCP_RESET) {
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vector = 0;
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} else if (env->intsrc != 0) {
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vector = ctz32(env->intsrc) + 1;
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}
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if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) {
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cpu_stb_data(env, env->sp--, (ret & 0x0000ff));
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cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8);
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cpu_stb_data(env, env->sp--, (ret & 0xff0000) >> 16);
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} else if (avr_feature(env, AVR_FEATURE_2_BYTE_PC)) {
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cpu_stb_data(env, env->sp--, (ret & 0x0000ff));
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cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8);
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} else {
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cpu_stb_data(env, env->sp--, (ret & 0x0000ff));
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}
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env->pc_w = base + vector * size;
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env->sregI = 0; /* clear Global Interrupt Flag */
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cs->exception_index = -1;
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}
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int avr_cpu_memory_rw_debug(CPUState *cs, vaddr addr, uint8_t *buf,
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int len, bool is_write)
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{
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return cpu_memory_rw_debug(cs, addr, buf, len, is_write);
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}
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hwaddr avr_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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{
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return addr; /* I assume 1:1 address correspondance */
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}
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bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr)
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{
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int prot = 0;
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MemTxAttrs attrs = {};
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uint32_t paddr;
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address &= TARGET_PAGE_MASK;
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if (mmu_idx == MMU_CODE_IDX) {
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/* access to code in flash */
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paddr = OFFSET_CODE + address;
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prot = PAGE_READ | PAGE_EXEC;
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if (paddr + TARGET_PAGE_SIZE > OFFSET_DATA) {
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error_report("execution left flash memory");
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abort();
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}
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} else if (address < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) {
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/*
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* access to CPU registers, exit and rebuilt this TB to use full access
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* incase it touches specially handled registers like SREG or SP
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*/
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AVRCPU *cpu = AVR_CPU(cs);
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CPUAVRState *env = &cpu->env;
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env->fullacc = 1;
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cpu_loop_exit_restore(cs, retaddr);
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} else {
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/* access to memory. nothing special */
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paddr = OFFSET_DATA + address;
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prot = PAGE_READ | PAGE_WRITE;
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}
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tlb_set_page_with_attrs(cs, address, paddr, attrs, prot,
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mmu_idx, TARGET_PAGE_SIZE);
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return true;
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}
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