Currently, the fdt is copied to the ROM after the reset vector. The firmware has to copy it to DRAM. Instead of this, directly copy the device tree to a pre-computed dram address. The device tree load address should be as far as possible from kernel and initrd images. That's why it is kept at the end of the DRAM or 4GB whichever is lesser. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Message-Id: <20200701183949.398134-3-atish.patra@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
752 lines
30 KiB
C
752 lines
30 KiB
C
/*
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* QEMU RISC-V Board Compatible with SiFive Freedom U SDK
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2017 SiFive, Inc.
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* Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
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*
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* Provides a board compatible with the SiFive Freedom U SDK:
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*
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* 0) UART
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* 1) CLINT (Core Level Interruptor)
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* 2) PLIC (Platform Level Interrupt Controller)
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* 3) PRCI (Power, Reset, Clock, Interrupt)
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* 4) GPIO (General Purpose Input/Output Controller)
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* 5) OTP (One-Time Programmable) memory with stored serial number
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* 6) GEM (Gigabit Ethernet Controller) and management block
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*
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* This board currently generates devicetree dynamically that indicates at least
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* two harts and up to five harts.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "qapi/visitor.h"
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#include "hw/boards.h"
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#include "hw/irq.h"
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#include "hw/loader.h"
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#include "hw/sysbus.h"
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#include "hw/char/serial.h"
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#include "hw/cpu/cluster.h"
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#include "hw/misc/unimp.h"
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#include "target/riscv/cpu.h"
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#include "hw/riscv/riscv_hart.h"
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#include "hw/riscv/sifive_plic.h"
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#include "hw/riscv/sifive_clint.h"
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#include "hw/riscv/sifive_uart.h"
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#include "hw/riscv/sifive_u.h"
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#include "hw/riscv/boot.h"
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#include "chardev/char.h"
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#include "net/eth.h"
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#include "sysemu/arch_init.h"
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#include "sysemu/device_tree.h"
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#include "sysemu/runstate.h"
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#include "sysemu/sysemu.h"
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#include <libfdt.h>
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#if defined(TARGET_RISCV32)
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# define BIOS_FILENAME "opensbi-riscv32-sifive_u-fw_jump.bin"
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#else
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# define BIOS_FILENAME "opensbi-riscv64-sifive_u-fw_jump.bin"
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#endif
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static const struct MemmapEntry {
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hwaddr base;
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hwaddr size;
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} sifive_u_memmap[] = {
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[SIFIVE_U_DEBUG] = { 0x0, 0x100 },
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[SIFIVE_U_MROM] = { 0x1000, 0x11000 },
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[SIFIVE_U_CLINT] = { 0x2000000, 0x10000 },
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[SIFIVE_U_L2LIM] = { 0x8000000, 0x2000000 },
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[SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 },
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[SIFIVE_U_PRCI] = { 0x10000000, 0x1000 },
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[SIFIVE_U_UART0] = { 0x10010000, 0x1000 },
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[SIFIVE_U_UART1] = { 0x10011000, 0x1000 },
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[SIFIVE_U_GPIO] = { 0x10060000, 0x1000 },
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[SIFIVE_U_OTP] = { 0x10070000, 0x1000 },
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[SIFIVE_U_GEM] = { 0x10090000, 0x2000 },
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[SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 },
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[SIFIVE_U_DMC] = { 0x100b0000, 0x10000 },
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[SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 },
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[SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
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};
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#define OTP_SERIAL 1
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#define GEM_REVISION 0x10070109
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static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
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uint64_t mem_size, const char *cmdline)
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{
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MachineState *ms = MACHINE(qdev_get_machine());
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void *fdt;
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int cpu;
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uint32_t *cells;
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char *nodename;
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char ethclk_names[] = "pclk\0hclk";
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uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
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uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
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fdt = s->fdt = create_device_tree(&s->fdt_size);
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if (!fdt) {
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error_report("create_device_tree() failed");
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exit(1);
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}
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qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00");
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qemu_fdt_setprop_string(fdt, "/", "compatible",
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"sifive,hifive-unleashed-a00");
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qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
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qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
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qemu_fdt_add_subnode(fdt, "/soc");
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qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
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qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
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qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
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qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
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hfclk_phandle = phandle++;
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nodename = g_strdup_printf("/hfclk");
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle);
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qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk");
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qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
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SIFIVE_U_HFCLK_FREQ);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
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qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
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g_free(nodename);
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rtcclk_phandle = phandle++;
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nodename = g_strdup_printf("/rtcclk");
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle);
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qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk");
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qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
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SIFIVE_U_RTCCLK_FREQ);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
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qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
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g_free(nodename);
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nodename = g_strdup_printf("/memory@%lx",
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(long)memmap[SIFIVE_U_DRAM].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base,
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mem_size >> 32, mem_size);
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qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
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g_free(nodename);
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qemu_fdt_add_subnode(fdt, "/cpus");
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qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
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SIFIVE_CLINT_TIMEBASE_FREQ);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
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for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) {
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int cpu_phandle = phandle++;
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nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
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char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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char *isa;
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qemu_fdt_add_subnode(fdt, nodename);
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/* cpu 0 is the management hart that does not have mmu */
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if (cpu != 0) {
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#if defined(TARGET_RISCV32)
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qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
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#else
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qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
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#endif
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isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]);
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} else {
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isa = riscv_isa_string(&s->soc.e_cpus.harts[0]);
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}
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qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
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qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
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qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
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qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
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qemu_fdt_add_subnode(fdt, intc);
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qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle);
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qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
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qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
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qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
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g_free(isa);
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g_free(intc);
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g_free(nodename);
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}
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cells = g_new0(uint32_t, ms->smp.cpus * 4);
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for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
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nodename =
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g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
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cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
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cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
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cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
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cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
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g_free(nodename);
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}
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nodename = g_strdup_printf("/soc/clint@%lx",
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(long)memmap[SIFIVE_U_CLINT].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[SIFIVE_U_CLINT].base,
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0x0, memmap[SIFIVE_U_CLINT].size);
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qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
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cells, ms->smp.cpus * sizeof(uint32_t) * 4);
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g_free(cells);
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g_free(nodename);
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nodename = g_strdup_printf("/soc/otp@%lx",
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(long)memmap[SIFIVE_U_OTP].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE);
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[SIFIVE_U_OTP].base,
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0x0, memmap[SIFIVE_U_OTP].size);
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qemu_fdt_setprop_string(fdt, nodename, "compatible",
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"sifive,fu540-c000-otp");
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g_free(nodename);
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prci_phandle = phandle++;
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nodename = g_strdup_printf("/soc/clock-controller@%lx",
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(long)memmap[SIFIVE_U_PRCI].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle);
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qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1);
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qemu_fdt_setprop_cells(fdt, nodename, "clocks",
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hfclk_phandle, rtcclk_phandle);
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[SIFIVE_U_PRCI].base,
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0x0, memmap[SIFIVE_U_PRCI].size);
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qemu_fdt_setprop_string(fdt, nodename, "compatible",
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"sifive,fu540-c000-prci");
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g_free(nodename);
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plic_phandle = phandle++;
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cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2);
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for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
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nodename =
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g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
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/* cpu 0 is the management hart that does not have S-mode */
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if (cpu == 0) {
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cells[0] = cpu_to_be32(intc_phandle);
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cells[1] = cpu_to_be32(IRQ_M_EXT);
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} else {
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cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle);
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cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT);
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cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
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cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT);
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}
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g_free(nodename);
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}
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nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
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(long)memmap[SIFIVE_U_PLIC].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
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qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
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qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
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cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t));
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[SIFIVE_U_PLIC].base,
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0x0, memmap[SIFIVE_U_PLIC].size);
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qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
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qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
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plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
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g_free(cells);
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g_free(nodename);
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gpio_phandle = phandle++;
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nodename = g_strdup_printf("/soc/gpio@%lx",
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(long)memmap[SIFIVE_U_GPIO].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle);
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qemu_fdt_setprop_cells(fdt, nodename, "clocks",
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prci_phandle, PRCI_CLK_TLCLK);
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qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2);
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qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
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qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2);
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qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0);
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[SIFIVE_U_GPIO].base,
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0x0, memmap[SIFIVE_U_GPIO].size);
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qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0,
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SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3,
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SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6,
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SIFIVE_U_GPIO_IRQ7, SIFIVE_U_GPIO_IRQ8, SIFIVE_U_GPIO_IRQ9,
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SIFIVE_U_GPIO_IRQ10, SIFIVE_U_GPIO_IRQ11, SIFIVE_U_GPIO_IRQ12,
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SIFIVE_U_GPIO_IRQ13, SIFIVE_U_GPIO_IRQ14, SIFIVE_U_GPIO_IRQ15);
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qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0");
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g_free(nodename);
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nodename = g_strdup_printf("/gpio-restart");
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cells(fdt, nodename, "gpios", gpio_phandle, 10, 1);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart");
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g_free(nodename);
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phy_phandle = phandle++;
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nodename = g_strdup_printf("/soc/ethernet@%lx",
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(long)memmap[SIFIVE_U_GEM].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_string(fdt, nodename, "compatible",
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"sifive,fu540-c000-gem");
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[SIFIVE_U_GEM].base,
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0x0, memmap[SIFIVE_U_GEM].size,
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0x0, memmap[SIFIVE_U_GEM_MGMT].base,
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0x0, memmap[SIFIVE_U_GEM_MGMT].size);
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qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
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qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
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qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle);
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qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
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qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
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qemu_fdt_setprop_cells(fdt, nodename, "clocks",
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prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL);
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qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names,
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sizeof(ethclk_names));
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qemu_fdt_setprop(fdt, nodename, "local-mac-address",
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s->soc.gem.conf.macaddr.a, ETH_ALEN);
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qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
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qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
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qemu_fdt_add_subnode(fdt, "/aliases");
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qemu_fdt_setprop_string(fdt, "/aliases", "ethernet0", nodename);
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g_free(nodename);
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nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
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|
(long)memmap[SIFIVE_U_GEM].base);
|
|
qemu_fdt_add_subnode(fdt, nodename);
|
|
qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle);
|
|
qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
|
|
g_free(nodename);
|
|
|
|
nodename = g_strdup_printf("/soc/serial@%lx",
|
|
(long)memmap[SIFIVE_U_UART0].base);
|
|
qemu_fdt_add_subnode(fdt, nodename);
|
|
qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
|
|
qemu_fdt_setprop_cells(fdt, nodename, "reg",
|
|
0x0, memmap[SIFIVE_U_UART0].base,
|
|
0x0, memmap[SIFIVE_U_UART0].size);
|
|
qemu_fdt_setprop_cells(fdt, nodename, "clocks",
|
|
prci_phandle, PRCI_CLK_TLCLK);
|
|
qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
|
|
qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ);
|
|
|
|
qemu_fdt_add_subnode(fdt, "/chosen");
|
|
qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
|
|
if (cmdline) {
|
|
qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
|
|
}
|
|
|
|
qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename);
|
|
|
|
g_free(nodename);
|
|
}
|
|
|
|
static void sifive_u_machine_reset(void *opaque, int n, int level)
|
|
{
|
|
/* gpio pin active low triggers reset */
|
|
if (!level) {
|
|
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
|
|
}
|
|
}
|
|
|
|
static void sifive_u_machine_init(MachineState *machine)
|
|
{
|
|
const struct MemmapEntry *memmap = sifive_u_memmap;
|
|
SiFiveUState *s = RISCV_U_MACHINE(machine);
|
|
MemoryRegion *system_memory = get_system_memory();
|
|
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
|
|
MemoryRegion *flash0 = g_new(MemoryRegion, 1);
|
|
target_ulong start_addr = memmap[SIFIVE_U_DRAM].base;
|
|
int i;
|
|
uint32_t fdt_load_addr;
|
|
|
|
/* Initialize SoC */
|
|
object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC);
|
|
object_property_set_uint(OBJECT(&s->soc), "serial", s->serial,
|
|
&error_abort);
|
|
qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
|
|
|
|
/* register RAM */
|
|
memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
|
|
machine->ram_size, &error_fatal);
|
|
memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base,
|
|
main_mem);
|
|
|
|
/* register QSPI0 Flash */
|
|
memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0",
|
|
memmap[SIFIVE_U_FLASH0].size, &error_fatal);
|
|
memory_region_add_subregion(system_memory, memmap[SIFIVE_U_FLASH0].base,
|
|
flash0);
|
|
|
|
/* register gpio-restart */
|
|
qdev_connect_gpio_out(DEVICE(&(s->soc.gpio)), 10,
|
|
qemu_allocate_irq(sifive_u_machine_reset, NULL, 0));
|
|
|
|
/* create device tree */
|
|
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
|
|
|
|
if (s->start_in_flash) {
|
|
/*
|
|
* If start_in_flash property is given, assign s->msel to a value
|
|
* that representing booting from QSPI0 memory-mapped flash.
|
|
*
|
|
* This also means that when both start_in_flash and msel properties
|
|
* are given, start_in_flash takes the precedence over msel.
|
|
*
|
|
* Note this is to keep backward compatibility not to break existing
|
|
* users that use start_in_flash property.
|
|
*/
|
|
s->msel = MSEL_MEMMAP_QSPI0_FLASH;
|
|
}
|
|
|
|
switch (s->msel) {
|
|
case MSEL_MEMMAP_QSPI0_FLASH:
|
|
start_addr = memmap[SIFIVE_U_FLASH0].base;
|
|
break;
|
|
case MSEL_L2LIM_QSPI0_FLASH:
|
|
case MSEL_L2LIM_QSPI2_SD:
|
|
start_addr = memmap[SIFIVE_U_L2LIM].base;
|
|
break;
|
|
default:
|
|
start_addr = memmap[SIFIVE_U_DRAM].base;
|
|
break;
|
|
}
|
|
|
|
riscv_find_and_load_firmware(machine, BIOS_FILENAME, start_addr, NULL);
|
|
|
|
if (machine->kernel_filename) {
|
|
uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
|
|
NULL);
|
|
|
|
if (machine->initrd_filename) {
|
|
hwaddr start;
|
|
hwaddr end = riscv_load_initrd(machine->initrd_filename,
|
|
machine->ram_size, kernel_entry,
|
|
&start);
|
|
qemu_fdt_setprop_cell(s->fdt, "/chosen",
|
|
"linux,initrd-start", start);
|
|
qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
|
|
end);
|
|
}
|
|
}
|
|
|
|
/* Compute the fdt load address in dram */
|
|
fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DRAM].base,
|
|
machine->ram_size, s->fdt);
|
|
|
|
/* reset vector */
|
|
uint32_t reset_vec[11] = {
|
|
s->msel, /* MSEL pin state */
|
|
0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
|
|
0xf1402573, /* csrr a0, mhartid */
|
|
#if defined(TARGET_RISCV32)
|
|
0x0202a583, /* lw a1, 32(t0) */
|
|
0x0182a283, /* lw t0, 24(t0) */
|
|
#elif defined(TARGET_RISCV64)
|
|
0x0202b583, /* ld a1, 32(t0) */
|
|
0x0182b283, /* ld t0, 24(t0) */
|
|
#endif
|
|
0x00028067, /* jr t0 */
|
|
0x00000000,
|
|
start_addr, /* start: .dword */
|
|
0x00000000,
|
|
fdt_load_addr, /* fdt_laddr: .dword */
|
|
0x00000000,
|
|
/* dtb: */
|
|
};
|
|
|
|
/* copy in the reset vector in little_endian byte order */
|
|
for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
|
|
reset_vec[i] = cpu_to_le32(reset_vec[i]);
|
|
}
|
|
rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
|
|
memmap[SIFIVE_U_MROM].base, &address_space_memory);
|
|
}
|
|
|
|
static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp)
|
|
{
|
|
SiFiveUState *s = RISCV_U_MACHINE(obj);
|
|
|
|
return s->start_in_flash;
|
|
}
|
|
|
|
static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error **errp)
|
|
{
|
|
SiFiveUState *s = RISCV_U_MACHINE(obj);
|
|
|
|
s->start_in_flash = value;
|
|
}
|
|
|
|
static void sifive_u_machine_get_uint32_prop(Object *obj, Visitor *v,
|
|
const char *name, void *opaque,
|
|
Error **errp)
|
|
{
|
|
visit_type_uint32(v, name, (uint32_t *)opaque, errp);
|
|
}
|
|
|
|
static void sifive_u_machine_set_uint32_prop(Object *obj, Visitor *v,
|
|
const char *name, void *opaque,
|
|
Error **errp)
|
|
{
|
|
visit_type_uint32(v, name, (uint32_t *)opaque, errp);
|
|
}
|
|
|
|
static void sifive_u_machine_instance_init(Object *obj)
|
|
{
|
|
SiFiveUState *s = RISCV_U_MACHINE(obj);
|
|
|
|
s->start_in_flash = false;
|
|
object_property_add_bool(obj, "start-in-flash",
|
|
sifive_u_machine_get_start_in_flash,
|
|
sifive_u_machine_set_start_in_flash);
|
|
object_property_set_description(obj, "start-in-flash",
|
|
"Set on to tell QEMU's ROM to jump to "
|
|
"flash. Otherwise QEMU will jump to DRAM "
|
|
"or L2LIM depending on the msel value");
|
|
|
|
s->msel = 0;
|
|
object_property_add(obj, "msel", "uint32",
|
|
sifive_u_machine_get_uint32_prop,
|
|
sifive_u_machine_set_uint32_prop, NULL, &s->msel);
|
|
object_property_set_description(obj, "msel",
|
|
"Mode Select (MSEL[3:0]) pin state");
|
|
|
|
s->serial = OTP_SERIAL;
|
|
object_property_add(obj, "serial", "uint32",
|
|
sifive_u_machine_get_uint32_prop,
|
|
sifive_u_machine_set_uint32_prop, NULL, &s->serial);
|
|
object_property_set_description(obj, "serial", "Board serial number");
|
|
}
|
|
|
|
static void sifive_u_machine_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
mc->desc = "RISC-V Board compatible with SiFive U SDK";
|
|
mc->init = sifive_u_machine_init;
|
|
mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
|
|
mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
|
|
mc->default_cpus = mc->min_cpus;
|
|
}
|
|
|
|
static const TypeInfo sifive_u_machine_typeinfo = {
|
|
.name = MACHINE_TYPE_NAME("sifive_u"),
|
|
.parent = TYPE_MACHINE,
|
|
.class_init = sifive_u_machine_class_init,
|
|
.instance_init = sifive_u_machine_instance_init,
|
|
.instance_size = sizeof(SiFiveUState),
|
|
};
|
|
|
|
static void sifive_u_machine_init_register_types(void)
|
|
{
|
|
type_register_static(&sifive_u_machine_typeinfo);
|
|
}
|
|
|
|
type_init(sifive_u_machine_init_register_types)
|
|
|
|
static void sifive_u_soc_instance_init(Object *obj)
|
|
{
|
|
MachineState *ms = MACHINE(qdev_get_machine());
|
|
SiFiveUSoCState *s = RISCV_U_SOC(obj);
|
|
|
|
object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER);
|
|
qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0);
|
|
|
|
object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus,
|
|
TYPE_RISCV_HART_ARRAY);
|
|
qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
|
|
qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
|
|
qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU);
|
|
|
|
object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);
|
|
qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
|
|
|
|
object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus,
|
|
TYPE_RISCV_HART_ARRAY);
|
|
qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
|
|
qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
|
|
qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", SIFIVE_U_CPU);
|
|
|
|
object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI);
|
|
object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP);
|
|
object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM);
|
|
object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO);
|
|
}
|
|
|
|
static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
MachineState *ms = MACHINE(qdev_get_machine());
|
|
SiFiveUSoCState *s = RISCV_U_SOC(dev);
|
|
const struct MemmapEntry *memmap = sifive_u_memmap;
|
|
MemoryRegion *system_memory = get_system_memory();
|
|
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
|
|
MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
|
|
char *plic_hart_config;
|
|
size_t plic_hart_config_len;
|
|
int i;
|
|
NICInfo *nd = &nd_table[0];
|
|
|
|
sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
|
|
sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort);
|
|
/*
|
|
* The cluster must be realized after the RISC-V hart array container,
|
|
* as the container's CPU object is only created on realize, and the
|
|
* CPU must exist and have been parented into the cluster before the
|
|
* cluster is realized.
|
|
*/
|
|
qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort);
|
|
qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort);
|
|
|
|
/* boot rom */
|
|
memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom",
|
|
memmap[SIFIVE_U_MROM].size, &error_fatal);
|
|
memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base,
|
|
mask_rom);
|
|
|
|
/*
|
|
* Add L2-LIM at reset size.
|
|
* This should be reduced in size as the L2 Cache Controller WayEnable
|
|
* register is incremented. Unfortunately I don't see a nice (or any) way
|
|
* to handle reducing or blocking out the L2 LIM while still allowing it
|
|
* be re returned to all enabled after a reset. For the time being, just
|
|
* leave it enabled all the time. This won't break anything, but will be
|
|
* too generous to misbehaving guests.
|
|
*/
|
|
memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim",
|
|
memmap[SIFIVE_U_L2LIM].size, &error_fatal);
|
|
memory_region_add_subregion(system_memory, memmap[SIFIVE_U_L2LIM].base,
|
|
l2lim_mem);
|
|
|
|
/* create PLIC hart topology configuration string */
|
|
plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) *
|
|
ms->smp.cpus;
|
|
plic_hart_config = g_malloc0(plic_hart_config_len);
|
|
for (i = 0; i < ms->smp.cpus; i++) {
|
|
if (i != 0) {
|
|
strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG,
|
|
plic_hart_config_len);
|
|
} else {
|
|
strncat(plic_hart_config, "M", plic_hart_config_len);
|
|
}
|
|
plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1);
|
|
}
|
|
|
|
/* MMIO */
|
|
s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base,
|
|
plic_hart_config,
|
|
SIFIVE_U_PLIC_NUM_SOURCES,
|
|
SIFIVE_U_PLIC_NUM_PRIORITIES,
|
|
SIFIVE_U_PLIC_PRIORITY_BASE,
|
|
SIFIVE_U_PLIC_PENDING_BASE,
|
|
SIFIVE_U_PLIC_ENABLE_BASE,
|
|
SIFIVE_U_PLIC_ENABLE_STRIDE,
|
|
SIFIVE_U_PLIC_CONTEXT_BASE,
|
|
SIFIVE_U_PLIC_CONTEXT_STRIDE,
|
|
memmap[SIFIVE_U_PLIC].size);
|
|
g_free(plic_hart_config);
|
|
sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
|
|
serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
|
|
sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
|
|
serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
|
|
sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
|
|
memmap[SIFIVE_U_CLINT].size, ms->smp.cpus,
|
|
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
|
|
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
|
|
return;
|
|
}
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base);
|
|
|
|
qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16);
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
|
|
return;
|
|
}
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_GPIO].base);
|
|
|
|
/* Pass all GPIOs to the SOC layer so they are available to the board */
|
|
qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
|
|
|
|
/* Connect GPIO interrupts to the PLIC */
|
|
for (i = 0; i < 16; i++) {
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i,
|
|
qdev_get_gpio_in(DEVICE(s->plic),
|
|
SIFIVE_U_GPIO_IRQ0 + i));
|
|
}
|
|
|
|
qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial);
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) {
|
|
return;
|
|
}
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base);
|
|
|
|
if (nd->used) {
|
|
qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
|
|
qdev_set_nic_properties(DEVICE(&s->gem), nd);
|
|
}
|
|
object_property_set_int(OBJECT(&s->gem), "revision", GEM_REVISION,
|
|
&error_abort);
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) {
|
|
return;
|
|
}
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
|
|
qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ));
|
|
|
|
create_unimplemented_device("riscv.sifive.u.gem-mgmt",
|
|
memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
|
|
|
|
create_unimplemented_device("riscv.sifive.u.dmc",
|
|
memmap[SIFIVE_U_DMC].base, memmap[SIFIVE_U_DMC].size);
|
|
}
|
|
|
|
static Property sifive_u_soc_props[] = {
|
|
DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL),
|
|
DEFINE_PROP_END_OF_LIST()
|
|
};
|
|
|
|
static void sifive_u_soc_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
device_class_set_props(dc, sifive_u_soc_props);
|
|
dc->realize = sifive_u_soc_realize;
|
|
/* Reason: Uses serial_hds in realize function, thus can't be used twice */
|
|
dc->user_creatable = false;
|
|
}
|
|
|
|
static const TypeInfo sifive_u_soc_type_info = {
|
|
.name = TYPE_RISCV_U_SOC,
|
|
.parent = TYPE_DEVICE,
|
|
.instance_size = sizeof(SiFiveUSoCState),
|
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.instance_init = sifive_u_soc_instance_init,
|
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.class_init = sifive_u_soc_class_init,
|
|
};
|
|
|
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static void sifive_u_soc_register_types(void)
|
|
{
|
|
type_register_static(&sifive_u_soc_type_info);
|
|
}
|
|
|
|
type_init(sifive_u_soc_register_types)
|