arm_regime_using_lpae_format checks whether the LPAE extension is used for stage 1 translation regimes. MMU indexes not exclusively of a stage 1 regime won't work with this method. In case of ARMMMUIdx_S12NSE0 or ARMMMUIdx_S12NSE1, offset these values by ARMMMUIdx_S1NSE0 to get the right index indicating a stage 1 translation regime. Rename also the function to arm_s1_regime_using_lpae_format and update the comments to reflect the change. Signed-off-by: Alvise Rigo <a.rigo@virtualopensystems.com> Message-id: 1452854262-19550-1-git-send-email-a.rigo@virtualopensystems.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
1045 lines
29 KiB
C
1045 lines
29 KiB
C
/*
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* ARM helper routines
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*
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* Copyright (c) 2005-2007 CodeSourcery, LLC
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h"
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#include "exec/helper-proto.h"
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#include "internals.h"
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#include "exec/cpu_ldst.h"
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#define SIGNBIT (uint32_t)0x80000000
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#define SIGNBIT64 ((uint64_t)1 << 63)
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static void raise_exception(CPUARMState *env, uint32_t excp,
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uint32_t syndrome, uint32_t target_el)
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{
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CPUState *cs = CPU(arm_env_get_cpu(env));
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assert(!excp_is_internal(excp));
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cs->exception_index = excp;
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env->exception.syndrome = syndrome;
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env->exception.target_el = target_el;
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cpu_loop_exit(cs);
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}
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static int exception_target_el(CPUARMState *env)
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{
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int target_el = MAX(1, arm_current_el(env));
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/* No such thing as secure EL1 if EL3 is aarch32, so update the target EL
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* to EL3 in this case.
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*/
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if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) {
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target_el = 3;
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}
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return target_el;
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}
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uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def,
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uint32_t rn, uint32_t maxindex)
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{
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uint32_t val;
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uint32_t tmp;
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int index;
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int shift;
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uint64_t *table;
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table = (uint64_t *)&env->vfp.regs[rn];
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val = 0;
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for (shift = 0; shift < 32; shift += 8) {
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index = (ireg >> shift) & 0xff;
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if (index < maxindex) {
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tmp = (table[index >> 3] >> ((index & 7) << 3)) & 0xff;
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val |= tmp << shift;
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} else {
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val |= def & (0xff << shift);
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}
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}
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return val;
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}
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#if !defined(CONFIG_USER_ONLY)
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/* try to fill the TLB and return an exception if error. If retaddr is
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* NULL, it means that the function was called in C code (i.e. not
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* from generated code or from helper.c)
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*/
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void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
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uintptr_t retaddr)
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{
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bool ret;
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uint32_t fsr = 0;
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ARMMMUFaultInfo fi = {};
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ret = arm_tlb_fill(cs, addr, is_write, mmu_idx, &fsr, &fi);
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if (unlikely(ret)) {
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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uint32_t syn, exc;
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unsigned int target_el;
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bool same_el;
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if (retaddr) {
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/* now we have a real cpu fault */
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cpu_restore_state(cs, retaddr);
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}
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target_el = exception_target_el(env);
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if (fi.stage2) {
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target_el = 2;
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env->cp15.hpfar_el2 = extract64(fi.s2addr, 12, 47) << 4;
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}
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same_el = arm_current_el(env) == target_el;
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/* AArch64 syndrome does not have an LPAE bit */
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syn = fsr & ~(1 << 9);
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/* For insn and data aborts we assume there is no instruction syndrome
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* information; this is always true for exceptions reported to EL1.
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*/
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if (is_write == 2) {
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syn = syn_insn_abort(same_el, 0, fi.s1ptw, syn);
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exc = EXCP_PREFETCH_ABORT;
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} else {
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syn = syn_data_abort(same_el, 0, 0, fi.s1ptw, is_write == 1, syn);
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if (is_write == 1 && arm_feature(env, ARM_FEATURE_V6)) {
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fsr |= (1 << 11);
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}
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exc = EXCP_DATA_ABORT;
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}
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env->exception.vaddress = addr;
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env->exception.fsr = fsr;
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raise_exception(env, exc, syn, target_el);
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}
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}
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/* Raise a data fault alignment exception for the specified virtual address */
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void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, int is_write,
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int is_user, uintptr_t retaddr)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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int target_el;
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bool same_el;
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if (retaddr) {
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/* now we have a real cpu fault */
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cpu_restore_state(cs, retaddr);
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}
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target_el = exception_target_el(env);
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same_el = (arm_current_el(env) == target_el);
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env->exception.vaddress = vaddr;
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/* the DFSR for an alignment fault depends on whether we're using
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* the LPAE long descriptor format, or the short descriptor format
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*/
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if (arm_s1_regime_using_lpae_format(env, cpu_mmu_index(env, false))) {
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env->exception.fsr = 0x21;
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} else {
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env->exception.fsr = 0x1;
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}
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if (is_write == 1 && arm_feature(env, ARM_FEATURE_V6)) {
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env->exception.fsr |= (1 << 11);
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}
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raise_exception(env, EXCP_DATA_ABORT,
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syn_data_abort(same_el, 0, 0, 0, is_write == 1, 0x21),
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target_el);
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}
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#endif /* !defined(CONFIG_USER_ONLY) */
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uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b)
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{
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uint32_t res = a + b;
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if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT))
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env->QF = 1;
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return res;
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}
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uint32_t HELPER(add_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
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{
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uint32_t res = a + b;
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if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT)) {
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env->QF = 1;
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res = ~(((int32_t)a >> 31) ^ SIGNBIT);
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}
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return res;
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}
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uint32_t HELPER(sub_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
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{
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uint32_t res = a - b;
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if (((res ^ a) & SIGNBIT) && ((a ^ b) & SIGNBIT)) {
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env->QF = 1;
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res = ~(((int32_t)a >> 31) ^ SIGNBIT);
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}
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return res;
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}
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uint32_t HELPER(double_saturate)(CPUARMState *env, int32_t val)
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{
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uint32_t res;
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if (val >= 0x40000000) {
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res = ~SIGNBIT;
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env->QF = 1;
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} else if (val <= (int32_t)0xc0000000) {
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res = SIGNBIT;
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env->QF = 1;
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} else {
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res = val << 1;
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}
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return res;
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}
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uint32_t HELPER(add_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
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{
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uint32_t res = a + b;
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if (res < a) {
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env->QF = 1;
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res = ~0;
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}
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return res;
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}
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uint32_t HELPER(sub_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
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{
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uint32_t res = a - b;
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if (res > a) {
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env->QF = 1;
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res = 0;
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}
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return res;
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}
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/* Signed saturation. */
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static inline uint32_t do_ssat(CPUARMState *env, int32_t val, int shift)
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{
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int32_t top;
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uint32_t mask;
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top = val >> shift;
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mask = (1u << shift) - 1;
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if (top > 0) {
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env->QF = 1;
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return mask;
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} else if (top < -1) {
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env->QF = 1;
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return ~mask;
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}
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return val;
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}
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/* Unsigned saturation. */
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static inline uint32_t do_usat(CPUARMState *env, int32_t val, int shift)
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{
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uint32_t max;
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max = (1u << shift) - 1;
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if (val < 0) {
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env->QF = 1;
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return 0;
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} else if (val > max) {
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env->QF = 1;
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return max;
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}
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return val;
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}
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/* Signed saturate. */
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uint32_t HELPER(ssat)(CPUARMState *env, uint32_t x, uint32_t shift)
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{
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return do_ssat(env, x, shift);
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}
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/* Dual halfword signed saturate. */
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uint32_t HELPER(ssat16)(CPUARMState *env, uint32_t x, uint32_t shift)
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{
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uint32_t res;
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res = (uint16_t)do_ssat(env, (int16_t)x, shift);
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res |= do_ssat(env, ((int32_t)x) >> 16, shift) << 16;
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return res;
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}
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/* Unsigned saturate. */
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uint32_t HELPER(usat)(CPUARMState *env, uint32_t x, uint32_t shift)
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{
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return do_usat(env, x, shift);
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}
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/* Dual halfword unsigned saturate. */
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uint32_t HELPER(usat16)(CPUARMState *env, uint32_t x, uint32_t shift)
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{
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uint32_t res;
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res = (uint16_t)do_usat(env, (int16_t)x, shift);
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res |= do_usat(env, ((int32_t)x) >> 16, shift) << 16;
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return res;
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}
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/* Function checks whether WFx (WFI/WFE) instructions are set up to be trapped.
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* The function returns the target EL (1-3) if the instruction is to be trapped;
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* otherwise it returns 0 indicating it is not trapped.
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*/
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static inline int check_wfx_trap(CPUARMState *env, bool is_wfe)
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{
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int cur_el = arm_current_el(env);
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uint64_t mask;
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/* If we are currently in EL0 then we need to check if SCTLR is set up for
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* WFx instructions being trapped to EL1. These trap bits don't exist in v7.
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*/
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if (cur_el < 1 && arm_feature(env, ARM_FEATURE_V8)) {
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int target_el;
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mask = is_wfe ? SCTLR_nTWE : SCTLR_nTWI;
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if (arm_is_secure_below_el3(env) && !arm_el_is_aa64(env, 3)) {
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/* Secure EL0 and Secure PL1 is at EL3 */
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target_el = 3;
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} else {
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target_el = 1;
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}
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if (!(env->cp15.sctlr_el[target_el] & mask)) {
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return target_el;
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}
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}
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/* We are not trapping to EL1; trap to EL2 if HCR_EL2 requires it
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* No need for ARM_FEATURE check as if HCR_EL2 doesn't exist the
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* bits will be zero indicating no trap.
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*/
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if (cur_el < 2 && !arm_is_secure(env)) {
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mask = (is_wfe) ? HCR_TWE : HCR_TWI;
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if (env->cp15.hcr_el2 & mask) {
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return 2;
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}
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}
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/* We are not trapping to EL1 or EL2; trap to EL3 if SCR_EL3 requires it */
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if (cur_el < 3) {
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mask = (is_wfe) ? SCR_TWE : SCR_TWI;
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if (env->cp15.scr_el3 & mask) {
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return 3;
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}
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}
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return 0;
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}
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void HELPER(wfi)(CPUARMState *env)
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{
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CPUState *cs = CPU(arm_env_get_cpu(env));
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int target_el = check_wfx_trap(env, false);
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if (cpu_has_work(cs)) {
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/* Don't bother to go into our "low power state" if
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* we would just wake up immediately.
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*/
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return;
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}
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if (target_el) {
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env->pc -= 4;
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raise_exception(env, EXCP_UDEF, syn_wfx(1, 0xe, 0), target_el);
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}
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cs->exception_index = EXCP_HLT;
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cs->halted = 1;
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cpu_loop_exit(cs);
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}
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void HELPER(wfe)(CPUARMState *env)
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{
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/* This is a hint instruction that is semantically different
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* from YIELD even though we currently implement it identically.
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* Don't actually halt the CPU, just yield back to top
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* level loop. This is not going into a "low power state"
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* (ie halting until some event occurs), so we never take
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* a configurable trap to a different exception level.
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*/
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HELPER(yield)(env);
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}
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void HELPER(yield)(CPUARMState *env)
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{
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ARMCPU *cpu = arm_env_get_cpu(env);
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CPUState *cs = CPU(cpu);
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/* This is a non-trappable hint instruction that generally indicates
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* that the guest is currently busy-looping. Yield control back to the
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* top level loop so that a more deserving VCPU has a chance to run.
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*/
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cs->exception_index = EXCP_YIELD;
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cpu_loop_exit(cs);
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}
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/* Raise an internal-to-QEMU exception. This is limited to only
|
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* those EXCP values which are special cases for QEMU to interrupt
|
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* execution and not to be used for exceptions which are passed to
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* the guest (those must all have syndrome information and thus should
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* use exception_with_syndrome).
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*/
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void HELPER(exception_internal)(CPUARMState *env, uint32_t excp)
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{
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CPUState *cs = CPU(arm_env_get_cpu(env));
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assert(excp_is_internal(excp));
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cs->exception_index = excp;
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cpu_loop_exit(cs);
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}
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|
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/* Raise an exception with the specified syndrome register value */
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void HELPER(exception_with_syndrome)(CPUARMState *env, uint32_t excp,
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uint32_t syndrome, uint32_t target_el)
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{
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raise_exception(env, excp, syndrome, target_el);
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}
|
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|
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uint32_t HELPER(cpsr_read)(CPUARMState *env)
|
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{
|
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return cpsr_read(env) & ~(CPSR_EXEC | CPSR_RESERVED);
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}
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|
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void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask)
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{
|
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cpsr_write(env, val, mask);
|
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}
|
|
|
|
/* Access to user mode registers from privileged modes. */
|
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uint32_t HELPER(get_user_reg)(CPUARMState *env, uint32_t regno)
|
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{
|
|
uint32_t val;
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|
|
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if (regno == 13) {
|
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val = env->banked_r13[BANK_USRSYS];
|
|
} else if (regno == 14) {
|
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val = env->banked_r14[BANK_USRSYS];
|
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} else if (regno >= 8
|
|
&& (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) {
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val = env->usr_regs[regno - 8];
|
|
} else {
|
|
val = env->regs[regno];
|
|
}
|
|
return val;
|
|
}
|
|
|
|
void HELPER(set_user_reg)(CPUARMState *env, uint32_t regno, uint32_t val)
|
|
{
|
|
if (regno == 13) {
|
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env->banked_r13[BANK_USRSYS] = val;
|
|
} else if (regno == 14) {
|
|
env->banked_r14[BANK_USRSYS] = val;
|
|
} else if (regno >= 8
|
|
&& (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) {
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|
env->usr_regs[regno - 8] = val;
|
|
} else {
|
|
env->regs[regno] = val;
|
|
}
|
|
}
|
|
|
|
void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome)
|
|
{
|
|
const ARMCPRegInfo *ri = rip;
|
|
int target_el;
|
|
|
|
if (arm_feature(env, ARM_FEATURE_XSCALE) && ri->cp < 14
|
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&& extract32(env->cp15.c15_cpar, ri->cp, 1) == 0) {
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raise_exception(env, EXCP_UDEF, syndrome, exception_target_el(env));
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}
|
|
|
|
if (!ri->accessfn) {
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return;
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}
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|
|
|
switch (ri->accessfn(env, ri)) {
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case CP_ACCESS_OK:
|
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return;
|
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case CP_ACCESS_TRAP:
|
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target_el = exception_target_el(env);
|
|
break;
|
|
case CP_ACCESS_TRAP_EL2:
|
|
/* Requesting a trap to EL2 when we're in EL3 or S-EL0/1 is
|
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* a bug in the access function.
|
|
*/
|
|
assert(!arm_is_secure(env) && arm_current_el(env) != 3);
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target_el = 2;
|
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break;
|
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case CP_ACCESS_TRAP_EL3:
|
|
target_el = 3;
|
|
break;
|
|
case CP_ACCESS_TRAP_UNCATEGORIZED:
|
|
target_el = exception_target_el(env);
|
|
syndrome = syn_uncategorized();
|
|
break;
|
|
case CP_ACCESS_TRAP_UNCATEGORIZED_EL2:
|
|
target_el = 2;
|
|
syndrome = syn_uncategorized();
|
|
break;
|
|
case CP_ACCESS_TRAP_UNCATEGORIZED_EL3:
|
|
target_el = 3;
|
|
syndrome = syn_uncategorized();
|
|
break;
|
|
default:
|
|
g_assert_not_reached();
|
|
}
|
|
|
|
raise_exception(env, EXCP_UDEF, syndrome, target_el);
|
|
}
|
|
|
|
void HELPER(set_cp_reg)(CPUARMState *env, void *rip, uint32_t value)
|
|
{
|
|
const ARMCPRegInfo *ri = rip;
|
|
|
|
ri->writefn(env, ri, value);
|
|
}
|
|
|
|
uint32_t HELPER(get_cp_reg)(CPUARMState *env, void *rip)
|
|
{
|
|
const ARMCPRegInfo *ri = rip;
|
|
|
|
return ri->readfn(env, ri);
|
|
}
|
|
|
|
void HELPER(set_cp_reg64)(CPUARMState *env, void *rip, uint64_t value)
|
|
{
|
|
const ARMCPRegInfo *ri = rip;
|
|
|
|
ri->writefn(env, ri, value);
|
|
}
|
|
|
|
uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip)
|
|
{
|
|
const ARMCPRegInfo *ri = rip;
|
|
|
|
return ri->readfn(env, ri);
|
|
}
|
|
|
|
void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op, uint32_t imm)
|
|
{
|
|
/* MSR_i to update PSTATE. This is OK from EL0 only if UMA is set.
|
|
* Note that SPSel is never OK from EL0; we rely on handle_msr_i()
|
|
* to catch that case at translate time.
|
|
*/
|
|
if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) {
|
|
uint32_t syndrome = syn_aa64_sysregtrap(0, extract32(op, 0, 3),
|
|
extract32(op, 3, 3), 4,
|
|
imm, 0x1f, 0);
|
|
raise_exception(env, EXCP_UDEF, syndrome, exception_target_el(env));
|
|
}
|
|
|
|
switch (op) {
|
|
case 0x05: /* SPSel */
|
|
update_spsel(env, imm);
|
|
break;
|
|
case 0x1e: /* DAIFSet */
|
|
env->daif |= (imm << 6) & PSTATE_DAIF;
|
|
break;
|
|
case 0x1f: /* DAIFClear */
|
|
env->daif &= ~((imm << 6) & PSTATE_DAIF);
|
|
break;
|
|
default:
|
|
g_assert_not_reached();
|
|
}
|
|
}
|
|
|
|
void HELPER(clear_pstate_ss)(CPUARMState *env)
|
|
{
|
|
env->pstate &= ~PSTATE_SS;
|
|
}
|
|
|
|
void HELPER(pre_hvc)(CPUARMState *env)
|
|
{
|
|
ARMCPU *cpu = arm_env_get_cpu(env);
|
|
int cur_el = arm_current_el(env);
|
|
/* FIXME: Use actual secure state. */
|
|
bool secure = false;
|
|
bool undef;
|
|
|
|
if (arm_is_psci_call(cpu, EXCP_HVC)) {
|
|
/* If PSCI is enabled and this looks like a valid PSCI call then
|
|
* that overrides the architecturally mandated HVC behaviour.
|
|
*/
|
|
return;
|
|
}
|
|
|
|
if (!arm_feature(env, ARM_FEATURE_EL2)) {
|
|
/* If EL2 doesn't exist, HVC always UNDEFs */
|
|
undef = true;
|
|
} else if (arm_feature(env, ARM_FEATURE_EL3)) {
|
|
/* EL3.HCE has priority over EL2.HCD. */
|
|
undef = !(env->cp15.scr_el3 & SCR_HCE);
|
|
} else {
|
|
undef = env->cp15.hcr_el2 & HCR_HCD;
|
|
}
|
|
|
|
/* In ARMv7 and ARMv8/AArch32, HVC is undef in secure state.
|
|
* For ARMv8/AArch64, HVC is allowed in EL3.
|
|
* Note that we've already trapped HVC from EL0 at translation
|
|
* time.
|
|
*/
|
|
if (secure && (!is_a64(env) || cur_el == 1)) {
|
|
undef = true;
|
|
}
|
|
|
|
if (undef) {
|
|
raise_exception(env, EXCP_UDEF, syn_uncategorized(),
|
|
exception_target_el(env));
|
|
}
|
|
}
|
|
|
|
void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome)
|
|
{
|
|
ARMCPU *cpu = arm_env_get_cpu(env);
|
|
int cur_el = arm_current_el(env);
|
|
bool secure = arm_is_secure(env);
|
|
bool smd = env->cp15.scr_el3 & SCR_SMD;
|
|
/* On ARMv8 AArch32, SMD only applies to NS state.
|
|
* On ARMv7 SMD only applies to NS state and only if EL2 is available.
|
|
* For ARMv7 non EL2, we force SMD to zero so we don't need to re-check
|
|
* the EL2 condition here.
|
|
*/
|
|
bool undef = is_a64(env) ? smd : (!secure && smd);
|
|
|
|
if (arm_is_psci_call(cpu, EXCP_SMC)) {
|
|
/* If PSCI is enabled and this looks like a valid PSCI call then
|
|
* that overrides the architecturally mandated SMC behaviour.
|
|
*/
|
|
return;
|
|
}
|
|
|
|
if (!arm_feature(env, ARM_FEATURE_EL3)) {
|
|
/* If we have no EL3 then SMC always UNDEFs */
|
|
undef = true;
|
|
} else if (!secure && cur_el == 1 && (env->cp15.hcr_el2 & HCR_TSC)) {
|
|
/* In NS EL1, HCR controlled routing to EL2 has priority over SMD. */
|
|
raise_exception(env, EXCP_HYP_TRAP, syndrome, 2);
|
|
}
|
|
|
|
if (undef) {
|
|
raise_exception(env, EXCP_UDEF, syn_uncategorized(),
|
|
exception_target_el(env));
|
|
}
|
|
}
|
|
|
|
void HELPER(exception_return)(CPUARMState *env)
|
|
{
|
|
int cur_el = arm_current_el(env);
|
|
unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el);
|
|
uint32_t spsr = env->banked_spsr[spsr_idx];
|
|
int new_el;
|
|
|
|
aarch64_save_sp(env, cur_el);
|
|
|
|
env->exclusive_addr = -1;
|
|
|
|
/* We must squash the PSTATE.SS bit to zero unless both of the
|
|
* following hold:
|
|
* 1. debug exceptions are currently disabled
|
|
* 2. singlestep will be active in the EL we return to
|
|
* We check 1 here and 2 after we've done the pstate/cpsr write() to
|
|
* transition to the EL we're going to.
|
|
*/
|
|
if (arm_generate_debug_exceptions(env)) {
|
|
spsr &= ~PSTATE_SS;
|
|
}
|
|
|
|
if (spsr & PSTATE_nRW) {
|
|
/* TODO: We currently assume EL1/2/3 are running in AArch64. */
|
|
env->aarch64 = 0;
|
|
new_el = 0;
|
|
env->uncached_cpsr = 0x10;
|
|
cpsr_write(env, spsr, ~0);
|
|
if (!arm_singlestep_active(env)) {
|
|
env->uncached_cpsr &= ~PSTATE_SS;
|
|
}
|
|
aarch64_sync_64_to_32(env);
|
|
|
|
env->regs[15] = env->elr_el[1] & ~0x1;
|
|
} else {
|
|
new_el = extract32(spsr, 2, 2);
|
|
if (new_el > cur_el
|
|
|| (new_el == 2 && !arm_feature(env, ARM_FEATURE_EL2))) {
|
|
/* Disallow return to an EL which is unimplemented or higher
|
|
* than the current one.
|
|
*/
|
|
goto illegal_return;
|
|
}
|
|
if (extract32(spsr, 1, 1)) {
|
|
/* Return with reserved M[1] bit set */
|
|
goto illegal_return;
|
|
}
|
|
if (new_el == 0 && (spsr & PSTATE_SP)) {
|
|
/* Return to EL0 with M[0] bit set */
|
|
goto illegal_return;
|
|
}
|
|
env->aarch64 = 1;
|
|
pstate_write(env, spsr);
|
|
if (!arm_singlestep_active(env)) {
|
|
env->pstate &= ~PSTATE_SS;
|
|
}
|
|
aarch64_restore_sp(env, new_el);
|
|
env->pc = env->elr_el[cur_el];
|
|
}
|
|
|
|
return;
|
|
|
|
illegal_return:
|
|
/* Illegal return events of various kinds have architecturally
|
|
* mandated behaviour:
|
|
* restore NZCV and DAIF from SPSR_ELx
|
|
* set PSTATE.IL
|
|
* restore PC from ELR_ELx
|
|
* no change to exception level, execution state or stack pointer
|
|
*/
|
|
env->pstate |= PSTATE_IL;
|
|
env->pc = env->elr_el[cur_el];
|
|
spsr &= PSTATE_NZCV | PSTATE_DAIF;
|
|
spsr |= pstate_read(env) & ~(PSTATE_NZCV | PSTATE_DAIF);
|
|
pstate_write(env, spsr);
|
|
if (!arm_singlestep_active(env)) {
|
|
env->pstate &= ~PSTATE_SS;
|
|
}
|
|
}
|
|
|
|
/* Return true if the linked breakpoint entry lbn passes its checks */
|
|
static bool linked_bp_matches(ARMCPU *cpu, int lbn)
|
|
{
|
|
CPUARMState *env = &cpu->env;
|
|
uint64_t bcr = env->cp15.dbgbcr[lbn];
|
|
int brps = extract32(cpu->dbgdidr, 24, 4);
|
|
int ctx_cmps = extract32(cpu->dbgdidr, 20, 4);
|
|
int bt;
|
|
uint32_t contextidr;
|
|
|
|
/* Links to unimplemented or non-context aware breakpoints are
|
|
* CONSTRAINED UNPREDICTABLE: either behave as if disabled, or
|
|
* as if linked to an UNKNOWN context-aware breakpoint (in which
|
|
* case DBGWCR<n>_EL1.LBN must indicate that breakpoint).
|
|
* We choose the former.
|
|
*/
|
|
if (lbn > brps || lbn < (brps - ctx_cmps)) {
|
|
return false;
|
|
}
|
|
|
|
bcr = env->cp15.dbgbcr[lbn];
|
|
|
|
if (extract64(bcr, 0, 1) == 0) {
|
|
/* Linked breakpoint disabled : generate no events */
|
|
return false;
|
|
}
|
|
|
|
bt = extract64(bcr, 20, 4);
|
|
|
|
/* We match the whole register even if this is AArch32 using the
|
|
* short descriptor format (in which case it holds both PROCID and ASID),
|
|
* since we don't implement the optional v7 context ID masking.
|
|
*/
|
|
contextidr = extract64(env->cp15.contextidr_el[1], 0, 32);
|
|
|
|
switch (bt) {
|
|
case 3: /* linked context ID match */
|
|
if (arm_current_el(env) > 1) {
|
|
/* Context matches never fire in EL2 or (AArch64) EL3 */
|
|
return false;
|
|
}
|
|
return (contextidr == extract64(env->cp15.dbgbvr[lbn], 0, 32));
|
|
case 5: /* linked address mismatch (reserved in AArch64) */
|
|
case 9: /* linked VMID match (reserved if no EL2) */
|
|
case 11: /* linked context ID and VMID match (reserved if no EL2) */
|
|
default:
|
|
/* Links to Unlinked context breakpoints must generate no
|
|
* events; we choose to do the same for reserved values too.
|
|
*/
|
|
return false;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp)
|
|
{
|
|
CPUARMState *env = &cpu->env;
|
|
uint64_t cr;
|
|
int pac, hmc, ssc, wt, lbn;
|
|
/* Note that for watchpoints the check is against the CPU security
|
|
* state, not the S/NS attribute on the offending data access.
|
|
*/
|
|
bool is_secure = arm_is_secure(env);
|
|
int access_el = arm_current_el(env);
|
|
|
|
if (is_wp) {
|
|
CPUWatchpoint *wp = env->cpu_watchpoint[n];
|
|
|
|
if (!wp || !(wp->flags & BP_WATCHPOINT_HIT)) {
|
|
return false;
|
|
}
|
|
cr = env->cp15.dbgwcr[n];
|
|
if (wp->hitattrs.user) {
|
|
/* The LDRT/STRT/LDT/STT "unprivileged access" instructions should
|
|
* match watchpoints as if they were accesses done at EL0, even if
|
|
* the CPU is at EL1 or higher.
|
|
*/
|
|
access_el = 0;
|
|
}
|
|
} else {
|
|
uint64_t pc = is_a64(env) ? env->pc : env->regs[15];
|
|
|
|
if (!env->cpu_breakpoint[n] || env->cpu_breakpoint[n]->pc != pc) {
|
|
return false;
|
|
}
|
|
cr = env->cp15.dbgbcr[n];
|
|
}
|
|
/* The WATCHPOINT_HIT flag guarantees us that the watchpoint is
|
|
* enabled and that the address and access type match; for breakpoints
|
|
* we know the address matched; check the remaining fields, including
|
|
* linked breakpoints. We rely on WCR and BCR having the same layout
|
|
* for the LBN, SSC, HMC, PAC/PMC and is-linked fields.
|
|
* Note that some combinations of {PAC, HMC, SSC} are reserved and
|
|
* must act either like some valid combination or as if the watchpoint
|
|
* were disabled. We choose the former, and use this together with
|
|
* the fact that EL3 must always be Secure and EL2 must always be
|
|
* Non-Secure to simplify the code slightly compared to the full
|
|
* table in the ARM ARM.
|
|
*/
|
|
pac = extract64(cr, 1, 2);
|
|
hmc = extract64(cr, 13, 1);
|
|
ssc = extract64(cr, 14, 2);
|
|
|
|
switch (ssc) {
|
|
case 0:
|
|
break;
|
|
case 1:
|
|
case 3:
|
|
if (is_secure) {
|
|
return false;
|
|
}
|
|
break;
|
|
case 2:
|
|
if (!is_secure) {
|
|
return false;
|
|
}
|
|
break;
|
|
}
|
|
|
|
switch (access_el) {
|
|
case 3:
|
|
case 2:
|
|
if (!hmc) {
|
|
return false;
|
|
}
|
|
break;
|
|
case 1:
|
|
if (extract32(pac, 0, 1) == 0) {
|
|
return false;
|
|
}
|
|
break;
|
|
case 0:
|
|
if (extract32(pac, 1, 1) == 0) {
|
|
return false;
|
|
}
|
|
break;
|
|
default:
|
|
g_assert_not_reached();
|
|
}
|
|
|
|
wt = extract64(cr, 20, 1);
|
|
lbn = extract64(cr, 16, 4);
|
|
|
|
if (wt && !linked_bp_matches(cpu, lbn)) {
|
|
return false;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
static bool check_watchpoints(ARMCPU *cpu)
|
|
{
|
|
CPUARMState *env = &cpu->env;
|
|
int n;
|
|
|
|
/* If watchpoints are disabled globally or we can't take debug
|
|
* exceptions here then watchpoint firings are ignored.
|
|
*/
|
|
if (extract32(env->cp15.mdscr_el1, 15, 1) == 0
|
|
|| !arm_generate_debug_exceptions(env)) {
|
|
return false;
|
|
}
|
|
|
|
for (n = 0; n < ARRAY_SIZE(env->cpu_watchpoint); n++) {
|
|
if (bp_wp_matches(cpu, n, true)) {
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
static bool check_breakpoints(ARMCPU *cpu)
|
|
{
|
|
CPUARMState *env = &cpu->env;
|
|
int n;
|
|
|
|
/* If breakpoints are disabled globally or we can't take debug
|
|
* exceptions here then breakpoint firings are ignored.
|
|
*/
|
|
if (extract32(env->cp15.mdscr_el1, 15, 1) == 0
|
|
|| !arm_generate_debug_exceptions(env)) {
|
|
return false;
|
|
}
|
|
|
|
for (n = 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) {
|
|
if (bp_wp_matches(cpu, n, false)) {
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
void HELPER(check_breakpoints)(CPUARMState *env)
|
|
{
|
|
ARMCPU *cpu = arm_env_get_cpu(env);
|
|
|
|
if (check_breakpoints(cpu)) {
|
|
HELPER(exception_internal(env, EXCP_DEBUG));
|
|
}
|
|
}
|
|
|
|
void arm_debug_excp_handler(CPUState *cs)
|
|
{
|
|
/* Called by core code when a watchpoint or breakpoint fires;
|
|
* need to check which one and raise the appropriate exception.
|
|
*/
|
|
ARMCPU *cpu = ARM_CPU(cs);
|
|
CPUARMState *env = &cpu->env;
|
|
CPUWatchpoint *wp_hit = cs->watchpoint_hit;
|
|
|
|
if (wp_hit) {
|
|
if (wp_hit->flags & BP_CPU) {
|
|
cs->watchpoint_hit = NULL;
|
|
if (check_watchpoints(cpu)) {
|
|
bool wnr = (wp_hit->flags & BP_WATCHPOINT_HIT_WRITE) != 0;
|
|
bool same_el = arm_debug_target_el(env) == arm_current_el(env);
|
|
|
|
if (extended_addresses_enabled(env)) {
|
|
env->exception.fsr = (1 << 9) | 0x22;
|
|
} else {
|
|
env->exception.fsr = 0x2;
|
|
}
|
|
env->exception.vaddress = wp_hit->hitaddr;
|
|
raise_exception(env, EXCP_DATA_ABORT,
|
|
syn_watchpoint(same_el, 0, wnr),
|
|
arm_debug_target_el(env));
|
|
} else {
|
|
cpu_resume_from_signal(cs, NULL);
|
|
}
|
|
}
|
|
} else {
|
|
uint64_t pc = is_a64(env) ? env->pc : env->regs[15];
|
|
bool same_el = (arm_debug_target_el(env) == arm_current_el(env));
|
|
|
|
/* (1) GDB breakpoints should be handled first.
|
|
* (2) Do not raise a CPU exception if no CPU breakpoint has fired,
|
|
* since singlestep is also done by generating a debug internal
|
|
* exception.
|
|
*/
|
|
if (cpu_breakpoint_test(cs, pc, BP_GDB)
|
|
|| !cpu_breakpoint_test(cs, pc, BP_CPU)) {
|
|
return;
|
|
}
|
|
|
|
if (extended_addresses_enabled(env)) {
|
|
env->exception.fsr = (1 << 9) | 0x22;
|
|
} else {
|
|
env->exception.fsr = 0x2;
|
|
}
|
|
/* FAR is UNKNOWN, so doesn't need setting */
|
|
raise_exception(env, EXCP_PREFETCH_ABORT,
|
|
syn_breakpoint(same_el),
|
|
arm_debug_target_el(env));
|
|
}
|
|
}
|
|
|
|
/* ??? Flag setting arithmetic is awkward because we need to do comparisons.
|
|
The only way to do that in TCG is a conditional branch, which clobbers
|
|
all our temporaries. For now implement these as helper functions. */
|
|
|
|
/* Similarly for variable shift instructions. */
|
|
|
|
uint32_t HELPER(shl_cc)(CPUARMState *env, uint32_t x, uint32_t i)
|
|
{
|
|
int shift = i & 0xff;
|
|
if (shift >= 32) {
|
|
if (shift == 32)
|
|
env->CF = x & 1;
|
|
else
|
|
env->CF = 0;
|
|
return 0;
|
|
} else if (shift != 0) {
|
|
env->CF = (x >> (32 - shift)) & 1;
|
|
return x << shift;
|
|
}
|
|
return x;
|
|
}
|
|
|
|
uint32_t HELPER(shr_cc)(CPUARMState *env, uint32_t x, uint32_t i)
|
|
{
|
|
int shift = i & 0xff;
|
|
if (shift >= 32) {
|
|
if (shift == 32)
|
|
env->CF = (x >> 31) & 1;
|
|
else
|
|
env->CF = 0;
|
|
return 0;
|
|
} else if (shift != 0) {
|
|
env->CF = (x >> (shift - 1)) & 1;
|
|
return x >> shift;
|
|
}
|
|
return x;
|
|
}
|
|
|
|
uint32_t HELPER(sar_cc)(CPUARMState *env, uint32_t x, uint32_t i)
|
|
{
|
|
int shift = i & 0xff;
|
|
if (shift >= 32) {
|
|
env->CF = (x >> 31) & 1;
|
|
return (int32_t)x >> 31;
|
|
} else if (shift != 0) {
|
|
env->CF = (x >> (shift - 1)) & 1;
|
|
return (int32_t)x >> shift;
|
|
}
|
|
return x;
|
|
}
|
|
|
|
uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x, uint32_t i)
|
|
{
|
|
int shift1, shift;
|
|
shift1 = i & 0xff;
|
|
shift = shift1 & 0x1f;
|
|
if (shift == 0) {
|
|
if (shift1 != 0)
|
|
env->CF = (x >> 31) & 1;
|
|
return x;
|
|
} else {
|
|
env->CF = (x >> (shift - 1)) & 1;
|
|
return ((uint32_t)x >> shift) | (x << (32 - shift));
|
|
}
|
|
}
|