This is an autogenerated patch using scripts/switch-timer-api. Switch the entire code base to using the new timer API. Note this patch may introduce some line length issues. Signed-off-by: Alex Bligh <alex@alex.org.uk> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
912 lines
24 KiB
C
912 lines
24 KiB
C
/*
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* APIC support
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*
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* Copyright (c) 2004-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>
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*/
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#include "qemu/thread.h"
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#include "hw/i386/apic_internal.h"
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#include "hw/i386/apic.h"
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#include "hw/i386/ioapic.h"
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#include "hw/pci/msi.h"
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#include "qemu/host-utils.h"
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#include "trace.h"
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#include "hw/i386/pc.h"
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#include "hw/i386/apic-msidef.h"
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#define MAX_APIC_WORDS 8
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#define SYNC_FROM_VAPIC 0x1
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#define SYNC_TO_VAPIC 0x2
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#define SYNC_ISR_IRR_TO_VAPIC 0x4
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static APICCommonState *local_apics[MAX_APICS + 1];
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static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode);
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static void apic_update_irq(APICCommonState *s);
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static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
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uint8_t dest, uint8_t dest_mode);
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/* Find first bit starting from msb */
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static int apic_fls_bit(uint32_t value)
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{
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return 31 - clz32(value);
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}
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/* Find first bit starting from lsb */
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static int apic_ffs_bit(uint32_t value)
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{
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return ctz32(value);
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}
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static inline void apic_set_bit(uint32_t *tab, int index)
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{
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int i, mask;
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i = index >> 5;
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mask = 1 << (index & 0x1f);
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tab[i] |= mask;
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}
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static inline void apic_reset_bit(uint32_t *tab, int index)
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{
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int i, mask;
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i = index >> 5;
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mask = 1 << (index & 0x1f);
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tab[i] &= ~mask;
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}
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static inline int apic_get_bit(uint32_t *tab, int index)
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{
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int i, mask;
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i = index >> 5;
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mask = 1 << (index & 0x1f);
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return !!(tab[i] & mask);
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}
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/* return -1 if no bit is set */
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static int get_highest_priority_int(uint32_t *tab)
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{
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int i;
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for (i = 7; i >= 0; i--) {
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if (tab[i] != 0) {
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return i * 32 + apic_fls_bit(tab[i]);
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}
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}
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return -1;
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}
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static void apic_sync_vapic(APICCommonState *s, int sync_type)
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{
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VAPICState vapic_state;
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size_t length;
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off_t start;
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int vector;
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if (!s->vapic_paddr) {
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return;
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}
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if (sync_type & SYNC_FROM_VAPIC) {
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cpu_physical_memory_rw(s->vapic_paddr, (void *)&vapic_state,
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sizeof(vapic_state), 0);
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s->tpr = vapic_state.tpr;
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}
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if (sync_type & (SYNC_TO_VAPIC | SYNC_ISR_IRR_TO_VAPIC)) {
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start = offsetof(VAPICState, isr);
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length = offsetof(VAPICState, enabled) - offsetof(VAPICState, isr);
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if (sync_type & SYNC_TO_VAPIC) {
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assert(qemu_cpu_is_self(CPU(s->cpu)));
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vapic_state.tpr = s->tpr;
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vapic_state.enabled = 1;
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start = 0;
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length = sizeof(VAPICState);
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}
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vector = get_highest_priority_int(s->isr);
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if (vector < 0) {
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vector = 0;
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}
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vapic_state.isr = vector & 0xf0;
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vapic_state.zero = 0;
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vector = get_highest_priority_int(s->irr);
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if (vector < 0) {
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vector = 0;
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}
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vapic_state.irr = vector & 0xff;
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cpu_physical_memory_write_rom(s->vapic_paddr + start,
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((void *)&vapic_state) + start, length);
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}
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}
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static void apic_vapic_base_update(APICCommonState *s)
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{
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apic_sync_vapic(s, SYNC_TO_VAPIC);
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}
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static void apic_local_deliver(APICCommonState *s, int vector)
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{
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uint32_t lvt = s->lvt[vector];
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int trigger_mode;
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trace_apic_local_deliver(vector, (lvt >> 8) & 7);
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if (lvt & APIC_LVT_MASKED)
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return;
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switch ((lvt >> 8) & 7) {
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case APIC_DM_SMI:
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cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_SMI);
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break;
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case APIC_DM_NMI:
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cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_NMI);
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break;
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case APIC_DM_EXTINT:
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cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HARD);
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break;
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case APIC_DM_FIXED:
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trigger_mode = APIC_TRIGGER_EDGE;
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if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
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(lvt & APIC_LVT_LEVEL_TRIGGER))
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trigger_mode = APIC_TRIGGER_LEVEL;
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apic_set_irq(s, lvt & 0xff, trigger_mode);
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}
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}
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void apic_deliver_pic_intr(DeviceState *d, int level)
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{
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APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
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if (level) {
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apic_local_deliver(s, APIC_LVT_LINT0);
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} else {
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uint32_t lvt = s->lvt[APIC_LVT_LINT0];
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switch ((lvt >> 8) & 7) {
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case APIC_DM_FIXED:
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if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
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break;
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apic_reset_bit(s->irr, lvt & 0xff);
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/* fall through */
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case APIC_DM_EXTINT:
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cpu_reset_interrupt(CPU(s->cpu), CPU_INTERRUPT_HARD);
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break;
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}
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}
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}
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static void apic_external_nmi(APICCommonState *s)
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{
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apic_local_deliver(s, APIC_LVT_LINT1);
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}
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#define foreach_apic(apic, deliver_bitmask, code) \
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{\
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int __i, __j, __mask;\
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for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
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__mask = deliver_bitmask[__i];\
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if (__mask) {\
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for(__j = 0; __j < 32; __j++) {\
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if (__mask & (1 << __j)) {\
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apic = local_apics[__i * 32 + __j];\
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if (apic) {\
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code;\
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}\
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}\
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}\
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}\
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}\
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}
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static void apic_bus_deliver(const uint32_t *deliver_bitmask,
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uint8_t delivery_mode, uint8_t vector_num,
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uint8_t trigger_mode)
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{
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APICCommonState *apic_iter;
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switch (delivery_mode) {
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case APIC_DM_LOWPRI:
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/* XXX: search for focus processor, arbitration */
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{
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int i, d;
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d = -1;
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for(i = 0; i < MAX_APIC_WORDS; i++) {
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if (deliver_bitmask[i]) {
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d = i * 32 + apic_ffs_bit(deliver_bitmask[i]);
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break;
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}
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}
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if (d >= 0) {
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apic_iter = local_apics[d];
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if (apic_iter) {
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apic_set_irq(apic_iter, vector_num, trigger_mode);
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}
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}
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}
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return;
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case APIC_DM_FIXED:
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break;
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case APIC_DM_SMI:
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foreach_apic(apic_iter, deliver_bitmask,
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cpu_interrupt(CPU(apic_iter->cpu), CPU_INTERRUPT_SMI)
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);
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return;
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case APIC_DM_NMI:
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foreach_apic(apic_iter, deliver_bitmask,
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cpu_interrupt(CPU(apic_iter->cpu), CPU_INTERRUPT_NMI)
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);
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return;
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case APIC_DM_INIT:
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/* normal INIT IPI sent to processors */
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foreach_apic(apic_iter, deliver_bitmask,
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cpu_interrupt(CPU(apic_iter->cpu),
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CPU_INTERRUPT_INIT)
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);
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return;
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case APIC_DM_EXTINT:
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/* handled in I/O APIC code */
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break;
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default:
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return;
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}
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foreach_apic(apic_iter, deliver_bitmask,
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apic_set_irq(apic_iter, vector_num, trigger_mode) );
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}
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void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode,
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uint8_t vector_num, uint8_t trigger_mode)
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{
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uint32_t deliver_bitmask[MAX_APIC_WORDS];
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trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num,
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trigger_mode);
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apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
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apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode);
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}
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static void apic_set_base(APICCommonState *s, uint64_t val)
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{
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s->apicbase = (val & 0xfffff000) |
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(s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
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/* if disabled, cannot be enabled again */
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if (!(val & MSR_IA32_APICBASE_ENABLE)) {
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s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
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cpu_clear_apic_feature(&s->cpu->env);
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s->spurious_vec &= ~APIC_SV_ENABLE;
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}
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}
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static void apic_set_tpr(APICCommonState *s, uint8_t val)
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{
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/* Updates from cr8 are ignored while the VAPIC is active */
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if (!s->vapic_paddr) {
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s->tpr = val << 4;
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apic_update_irq(s);
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}
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}
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static uint8_t apic_get_tpr(APICCommonState *s)
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{
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apic_sync_vapic(s, SYNC_FROM_VAPIC);
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return s->tpr >> 4;
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}
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static int apic_get_ppr(APICCommonState *s)
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{
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int tpr, isrv, ppr;
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tpr = (s->tpr >> 4);
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isrv = get_highest_priority_int(s->isr);
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if (isrv < 0)
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isrv = 0;
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isrv >>= 4;
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if (tpr >= isrv)
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ppr = s->tpr;
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else
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ppr = isrv << 4;
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return ppr;
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}
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static int apic_get_arb_pri(APICCommonState *s)
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{
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/* XXX: arbitration */
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return 0;
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}
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/*
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* <0 - low prio interrupt,
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* 0 - no interrupt,
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* >0 - interrupt number
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*/
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static int apic_irq_pending(APICCommonState *s)
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{
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int irrv, ppr;
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irrv = get_highest_priority_int(s->irr);
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if (irrv < 0) {
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return 0;
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}
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ppr = apic_get_ppr(s);
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if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) {
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return -1;
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}
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return irrv;
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}
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/* signal the CPU if an irq is pending */
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static void apic_update_irq(APICCommonState *s)
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{
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CPUState *cpu;
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if (!(s->spurious_vec & APIC_SV_ENABLE)) {
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return;
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}
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cpu = CPU(s->cpu);
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if (!qemu_cpu_is_self(cpu)) {
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cpu_interrupt(cpu, CPU_INTERRUPT_POLL);
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} else if (apic_irq_pending(s) > 0) {
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cpu_interrupt(cpu, CPU_INTERRUPT_HARD);
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}
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}
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void apic_poll_irq(DeviceState *d)
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{
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APICCommonState *s = APIC_COMMON(d);
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apic_sync_vapic(s, SYNC_FROM_VAPIC);
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apic_update_irq(s);
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}
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static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode)
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{
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apic_report_irq_delivered(!apic_get_bit(s->irr, vector_num));
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apic_set_bit(s->irr, vector_num);
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if (trigger_mode)
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apic_set_bit(s->tmr, vector_num);
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else
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apic_reset_bit(s->tmr, vector_num);
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if (s->vapic_paddr) {
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apic_sync_vapic(s, SYNC_ISR_IRR_TO_VAPIC);
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/*
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* The vcpu thread needs to see the new IRR before we pull its current
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* TPR value. That way, if we miss a lowering of the TRP, the guest
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* has the chance to notice the new IRR and poll for IRQs on its own.
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*/
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smp_wmb();
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apic_sync_vapic(s, SYNC_FROM_VAPIC);
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}
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apic_update_irq(s);
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}
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static void apic_eoi(APICCommonState *s)
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{
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int isrv;
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isrv = get_highest_priority_int(s->isr);
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if (isrv < 0)
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return;
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apic_reset_bit(s->isr, isrv);
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if (!(s->spurious_vec & APIC_SV_DIRECTED_IO) && apic_get_bit(s->tmr, isrv)) {
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ioapic_eoi_broadcast(isrv);
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}
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apic_sync_vapic(s, SYNC_FROM_VAPIC | SYNC_TO_VAPIC);
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apic_update_irq(s);
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}
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static int apic_find_dest(uint8_t dest)
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{
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APICCommonState *apic = local_apics[dest];
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int i;
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if (apic && apic->id == dest)
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return dest; /* shortcut in case apic->id == apic->idx */
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for (i = 0; i < MAX_APICS; i++) {
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apic = local_apics[i];
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if (apic && apic->id == dest)
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return i;
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if (!apic)
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break;
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}
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return -1;
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}
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static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
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uint8_t dest, uint8_t dest_mode)
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{
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APICCommonState *apic_iter;
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int i;
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if (dest_mode == 0) {
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if (dest == 0xff) {
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memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
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} else {
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int idx = apic_find_dest(dest);
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memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
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if (idx >= 0)
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apic_set_bit(deliver_bitmask, idx);
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}
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} else {
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/* XXX: cluster mode */
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memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
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for(i = 0; i < MAX_APICS; i++) {
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apic_iter = local_apics[i];
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if (apic_iter) {
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if (apic_iter->dest_mode == 0xf) {
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if (dest & apic_iter->log_dest)
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apic_set_bit(deliver_bitmask, i);
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} else if (apic_iter->dest_mode == 0x0) {
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if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
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(dest & apic_iter->log_dest & 0x0f)) {
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apic_set_bit(deliver_bitmask, i);
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}
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}
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} else {
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break;
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}
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}
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}
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}
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static void apic_startup(APICCommonState *s, int vector_num)
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{
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s->sipi_vector = vector_num;
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cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_SIPI);
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}
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void apic_sipi(DeviceState *d)
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{
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APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
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cpu_reset_interrupt(CPU(s->cpu), CPU_INTERRUPT_SIPI);
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if (!s->wait_for_sipi)
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return;
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cpu_x86_load_seg_cache_sipi(s->cpu, s->sipi_vector);
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s->wait_for_sipi = 0;
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}
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static void apic_deliver(DeviceState *d, uint8_t dest, uint8_t dest_mode,
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uint8_t delivery_mode, uint8_t vector_num,
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uint8_t trigger_mode)
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{
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APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
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uint32_t deliver_bitmask[MAX_APIC_WORDS];
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|
int dest_shorthand = (s->icr[0] >> 18) & 3;
|
|
APICCommonState *apic_iter;
|
|
|
|
switch (dest_shorthand) {
|
|
case 0:
|
|
apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
|
|
break;
|
|
case 1:
|
|
memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
|
|
apic_set_bit(deliver_bitmask, s->idx);
|
|
break;
|
|
case 2:
|
|
memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
|
|
break;
|
|
case 3:
|
|
memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
|
|
apic_reset_bit(deliver_bitmask, s->idx);
|
|
break;
|
|
}
|
|
|
|
switch (delivery_mode) {
|
|
case APIC_DM_INIT:
|
|
{
|
|
int trig_mode = (s->icr[0] >> 15) & 1;
|
|
int level = (s->icr[0] >> 14) & 1;
|
|
if (level == 0 && trig_mode == 1) {
|
|
foreach_apic(apic_iter, deliver_bitmask,
|
|
apic_iter->arb_id = apic_iter->id );
|
|
return;
|
|
}
|
|
}
|
|
break;
|
|
|
|
case APIC_DM_SIPI:
|
|
foreach_apic(apic_iter, deliver_bitmask,
|
|
apic_startup(apic_iter, vector_num) );
|
|
return;
|
|
}
|
|
|
|
apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode);
|
|
}
|
|
|
|
static bool apic_check_pic(APICCommonState *s)
|
|
{
|
|
if (!apic_accept_pic_intr(&s->busdev.qdev) || !pic_get_output(isa_pic)) {
|
|
return false;
|
|
}
|
|
apic_deliver_pic_intr(&s->busdev.qdev, 1);
|
|
return true;
|
|
}
|
|
|
|
int apic_get_interrupt(DeviceState *d)
|
|
{
|
|
APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
|
|
int intno;
|
|
|
|
/* if the APIC is installed or enabled, we let the 8259 handle the
|
|
IRQs */
|
|
if (!s)
|
|
return -1;
|
|
if (!(s->spurious_vec & APIC_SV_ENABLE))
|
|
return -1;
|
|
|
|
apic_sync_vapic(s, SYNC_FROM_VAPIC);
|
|
intno = apic_irq_pending(s);
|
|
|
|
if (intno == 0) {
|
|
apic_sync_vapic(s, SYNC_TO_VAPIC);
|
|
return -1;
|
|
} else if (intno < 0) {
|
|
apic_sync_vapic(s, SYNC_TO_VAPIC);
|
|
return s->spurious_vec & 0xff;
|
|
}
|
|
apic_reset_bit(s->irr, intno);
|
|
apic_set_bit(s->isr, intno);
|
|
apic_sync_vapic(s, SYNC_TO_VAPIC);
|
|
|
|
/* re-inject if there is still a pending PIC interrupt */
|
|
apic_check_pic(s);
|
|
|
|
apic_update_irq(s);
|
|
|
|
return intno;
|
|
}
|
|
|
|
int apic_accept_pic_intr(DeviceState *d)
|
|
{
|
|
APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
|
|
uint32_t lvt0;
|
|
|
|
if (!s)
|
|
return -1;
|
|
|
|
lvt0 = s->lvt[APIC_LVT_LINT0];
|
|
|
|
if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
|
|
(lvt0 & APIC_LVT_MASKED) == 0)
|
|
return 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static uint32_t apic_get_current_count(APICCommonState *s)
|
|
{
|
|
int64_t d;
|
|
uint32_t val;
|
|
d = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->initial_count_load_time) >>
|
|
s->count_shift;
|
|
if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
|
|
/* periodic */
|
|
val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
|
|
} else {
|
|
if (d >= s->initial_count)
|
|
val = 0;
|
|
else
|
|
val = s->initial_count - d;
|
|
}
|
|
return val;
|
|
}
|
|
|
|
static void apic_timer_update(APICCommonState *s, int64_t current_time)
|
|
{
|
|
if (apic_next_timer(s, current_time)) {
|
|
timer_mod(s->timer, s->next_time);
|
|
} else {
|
|
timer_del(s->timer);
|
|
}
|
|
}
|
|
|
|
static void apic_timer(void *opaque)
|
|
{
|
|
APICCommonState *s = opaque;
|
|
|
|
apic_local_deliver(s, APIC_LVT_TIMER);
|
|
apic_timer_update(s, s->next_time);
|
|
}
|
|
|
|
static uint32_t apic_mem_readb(void *opaque, hwaddr addr)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static uint32_t apic_mem_readw(void *opaque, hwaddr addr)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static void apic_mem_writeb(void *opaque, hwaddr addr, uint32_t val)
|
|
{
|
|
}
|
|
|
|
static void apic_mem_writew(void *opaque, hwaddr addr, uint32_t val)
|
|
{
|
|
}
|
|
|
|
static uint32_t apic_mem_readl(void *opaque, hwaddr addr)
|
|
{
|
|
DeviceState *d;
|
|
APICCommonState *s;
|
|
uint32_t val;
|
|
int index;
|
|
|
|
d = cpu_get_current_apic();
|
|
if (!d) {
|
|
return 0;
|
|
}
|
|
s = DO_UPCAST(APICCommonState, busdev.qdev, d);
|
|
|
|
index = (addr >> 4) & 0xff;
|
|
switch(index) {
|
|
case 0x02: /* id */
|
|
val = s->id << 24;
|
|
break;
|
|
case 0x03: /* version */
|
|
val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
|
|
break;
|
|
case 0x08:
|
|
apic_sync_vapic(s, SYNC_FROM_VAPIC);
|
|
if (apic_report_tpr_access) {
|
|
cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_READ);
|
|
}
|
|
val = s->tpr;
|
|
break;
|
|
case 0x09:
|
|
val = apic_get_arb_pri(s);
|
|
break;
|
|
case 0x0a:
|
|
/* ppr */
|
|
val = apic_get_ppr(s);
|
|
break;
|
|
case 0x0b:
|
|
val = 0;
|
|
break;
|
|
case 0x0d:
|
|
val = s->log_dest << 24;
|
|
break;
|
|
case 0x0e:
|
|
val = s->dest_mode << 28;
|
|
break;
|
|
case 0x0f:
|
|
val = s->spurious_vec;
|
|
break;
|
|
case 0x10 ... 0x17:
|
|
val = s->isr[index & 7];
|
|
break;
|
|
case 0x18 ... 0x1f:
|
|
val = s->tmr[index & 7];
|
|
break;
|
|
case 0x20 ... 0x27:
|
|
val = s->irr[index & 7];
|
|
break;
|
|
case 0x28:
|
|
val = s->esr;
|
|
break;
|
|
case 0x30:
|
|
case 0x31:
|
|
val = s->icr[index & 1];
|
|
break;
|
|
case 0x32 ... 0x37:
|
|
val = s->lvt[index - 0x32];
|
|
break;
|
|
case 0x38:
|
|
val = s->initial_count;
|
|
break;
|
|
case 0x39:
|
|
val = apic_get_current_count(s);
|
|
break;
|
|
case 0x3e:
|
|
val = s->divide_conf;
|
|
break;
|
|
default:
|
|
s->esr |= ESR_ILLEGAL_ADDRESS;
|
|
val = 0;
|
|
break;
|
|
}
|
|
trace_apic_mem_readl(addr, val);
|
|
return val;
|
|
}
|
|
|
|
static void apic_send_msi(hwaddr addr, uint32_t data)
|
|
{
|
|
uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
|
|
uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
|
|
uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
|
|
uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
|
|
uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
|
|
/* XXX: Ignore redirection hint. */
|
|
apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode);
|
|
}
|
|
|
|
static void apic_mem_writel(void *opaque, hwaddr addr, uint32_t val)
|
|
{
|
|
DeviceState *d;
|
|
APICCommonState *s;
|
|
int index = (addr >> 4) & 0xff;
|
|
if (addr > 0xfff || !index) {
|
|
/* MSI and MMIO APIC are at the same memory location,
|
|
* but actually not on the global bus: MSI is on PCI bus
|
|
* APIC is connected directly to the CPU.
|
|
* Mapping them on the global bus happens to work because
|
|
* MSI registers are reserved in APIC MMIO and vice versa. */
|
|
apic_send_msi(addr, val);
|
|
return;
|
|
}
|
|
|
|
d = cpu_get_current_apic();
|
|
if (!d) {
|
|
return;
|
|
}
|
|
s = DO_UPCAST(APICCommonState, busdev.qdev, d);
|
|
|
|
trace_apic_mem_writel(addr, val);
|
|
|
|
switch(index) {
|
|
case 0x02:
|
|
s->id = (val >> 24);
|
|
break;
|
|
case 0x03:
|
|
break;
|
|
case 0x08:
|
|
if (apic_report_tpr_access) {
|
|
cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_WRITE);
|
|
}
|
|
s->tpr = val;
|
|
apic_sync_vapic(s, SYNC_TO_VAPIC);
|
|
apic_update_irq(s);
|
|
break;
|
|
case 0x09:
|
|
case 0x0a:
|
|
break;
|
|
case 0x0b: /* EOI */
|
|
apic_eoi(s);
|
|
break;
|
|
case 0x0d:
|
|
s->log_dest = val >> 24;
|
|
break;
|
|
case 0x0e:
|
|
s->dest_mode = val >> 28;
|
|
break;
|
|
case 0x0f:
|
|
s->spurious_vec = val & 0x1ff;
|
|
apic_update_irq(s);
|
|
break;
|
|
case 0x10 ... 0x17:
|
|
case 0x18 ... 0x1f:
|
|
case 0x20 ... 0x27:
|
|
case 0x28:
|
|
break;
|
|
case 0x30:
|
|
s->icr[0] = val;
|
|
apic_deliver(d, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
|
|
(s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
|
|
(s->icr[0] >> 15) & 1);
|
|
break;
|
|
case 0x31:
|
|
s->icr[1] = val;
|
|
break;
|
|
case 0x32 ... 0x37:
|
|
{
|
|
int n = index - 0x32;
|
|
s->lvt[n] = val;
|
|
if (n == APIC_LVT_TIMER) {
|
|
apic_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
|
|
} else if (n == APIC_LVT_LINT0 && apic_check_pic(s)) {
|
|
apic_update_irq(s);
|
|
}
|
|
}
|
|
break;
|
|
case 0x38:
|
|
s->initial_count = val;
|
|
s->initial_count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
|
|
apic_timer_update(s, s->initial_count_load_time);
|
|
break;
|
|
case 0x39:
|
|
break;
|
|
case 0x3e:
|
|
{
|
|
int v;
|
|
s->divide_conf = val & 0xb;
|
|
v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
|
|
s->count_shift = (v + 1) & 7;
|
|
}
|
|
break;
|
|
default:
|
|
s->esr |= ESR_ILLEGAL_ADDRESS;
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void apic_pre_save(APICCommonState *s)
|
|
{
|
|
apic_sync_vapic(s, SYNC_FROM_VAPIC);
|
|
}
|
|
|
|
static void apic_post_load(APICCommonState *s)
|
|
{
|
|
if (s->timer_expiry != -1) {
|
|
timer_mod(s->timer, s->timer_expiry);
|
|
} else {
|
|
timer_del(s->timer);
|
|
}
|
|
}
|
|
|
|
static const MemoryRegionOps apic_io_ops = {
|
|
.old_mmio = {
|
|
.read = { apic_mem_readb, apic_mem_readw, apic_mem_readl, },
|
|
.write = { apic_mem_writeb, apic_mem_writew, apic_mem_writel, },
|
|
},
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
};
|
|
|
|
static void apic_init(APICCommonState *s)
|
|
{
|
|
memory_region_init_io(&s->io_memory, OBJECT(s), &apic_io_ops, s, "apic-msi",
|
|
APIC_SPACE_SIZE);
|
|
|
|
s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, apic_timer, s);
|
|
local_apics[s->idx] = s;
|
|
|
|
msi_supported = true;
|
|
}
|
|
|
|
static void apic_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
APICCommonClass *k = APIC_COMMON_CLASS(klass);
|
|
|
|
k->init = apic_init;
|
|
k->set_base = apic_set_base;
|
|
k->set_tpr = apic_set_tpr;
|
|
k->get_tpr = apic_get_tpr;
|
|
k->vapic_base_update = apic_vapic_base_update;
|
|
k->external_nmi = apic_external_nmi;
|
|
k->pre_save = apic_pre_save;
|
|
k->post_load = apic_post_load;
|
|
}
|
|
|
|
static const TypeInfo apic_info = {
|
|
.name = "apic",
|
|
.instance_size = sizeof(APICCommonState),
|
|
.parent = TYPE_APIC_COMMON,
|
|
.class_init = apic_class_init,
|
|
};
|
|
|
|
static void apic_register_types(void)
|
|
{
|
|
type_register_static(&apic_info);
|
|
}
|
|
|
|
type_init(apic_register_types)
|