git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@692 c046a42c-6fe2-441c-8c8c-71466251a162
358 lines
9.3 KiB
C
358 lines
9.3 KiB
C
/*
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* QEMU 8253/8254 interval timer emulation
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h"
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//#define DEBUG_PIT
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#define RW_STATE_LSB 0
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#define RW_STATE_MSB 1
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#define RW_STATE_WORD0 2
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#define RW_STATE_WORD1 3
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#define RW_STATE_LATCHED_WORD0 4
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#define RW_STATE_LATCHED_WORD1 5
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PITChannelState pit_channels[3];
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static void pit_irq_timer_update(PITChannelState *s, int64_t current_time);
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static int pit_get_count(PITChannelState *s)
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{
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uint64_t d;
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int counter;
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d = muldiv64(qemu_get_clock(vm_clock) - s->count_load_time, PIT_FREQ, ticks_per_sec);
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switch(s->mode) {
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case 0:
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case 1:
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case 4:
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case 5:
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counter = (s->count - d) & 0xffff;
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break;
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case 3:
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/* XXX: may be incorrect for odd counts */
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counter = s->count - ((2 * d) % s->count);
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break;
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default:
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counter = s->count - (d % s->count);
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break;
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}
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return counter;
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}
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/* get pit output bit */
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int pit_get_out(PITChannelState *s, int64_t current_time)
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{
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uint64_t d;
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int out;
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d = muldiv64(current_time - s->count_load_time, PIT_FREQ, ticks_per_sec);
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switch(s->mode) {
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default:
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case 0:
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out = (d >= s->count);
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break;
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case 1:
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out = (d < s->count);
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break;
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case 2:
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if ((d % s->count) == 0 && d != 0)
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out = 1;
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else
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out = 0;
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break;
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case 3:
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out = (d % s->count) < ((s->count + 1) >> 1);
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break;
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case 4:
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case 5:
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out = (d == s->count);
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break;
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}
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return out;
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}
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/* return -1 if no transition will occur. */
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static int64_t pit_get_next_transition_time(PITChannelState *s,
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int64_t current_time)
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{
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uint64_t d, next_time, base;
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int period2;
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d = muldiv64(current_time - s->count_load_time, PIT_FREQ, ticks_per_sec);
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switch(s->mode) {
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default:
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case 0:
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case 1:
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if (d < s->count)
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next_time = s->count;
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else
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return -1;
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break;
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case 2:
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base = (d / s->count) * s->count;
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if ((d - base) == 0 && d != 0)
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next_time = base + s->count;
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else
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next_time = base + s->count + 1;
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break;
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case 3:
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base = (d / s->count) * s->count;
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period2 = ((s->count + 1) >> 1);
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if ((d - base) < period2)
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next_time = base + period2;
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else
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next_time = base + s->count;
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break;
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case 4:
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case 5:
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if (d < s->count)
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next_time = s->count;
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else if (d == s->count)
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next_time = s->count + 1;
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else
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return -1;
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break;
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}
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/* convert to timer units */
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next_time = s->count_load_time + muldiv64(next_time, ticks_per_sec, PIT_FREQ);
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return next_time;
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}
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/* val must be 0 or 1 */
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void pit_set_gate(PITChannelState *s, int val)
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{
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switch(s->mode) {
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default:
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case 0:
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case 4:
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/* XXX: just disable/enable counting */
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break;
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case 1:
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case 5:
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if (s->gate < val) {
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/* restart counting on rising edge */
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s->count_load_time = qemu_get_clock(vm_clock);
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pit_irq_timer_update(s, s->count_load_time);
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}
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break;
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case 2:
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case 3:
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if (s->gate < val) {
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/* restart counting on rising edge */
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s->count_load_time = qemu_get_clock(vm_clock);
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pit_irq_timer_update(s, s->count_load_time);
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}
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/* XXX: disable/enable counting */
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break;
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}
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s->gate = val;
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}
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static inline void pit_load_count(PITChannelState *s, int val)
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{
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if (val == 0)
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val = 0x10000;
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s->count_load_time = qemu_get_clock(vm_clock);
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s->count = val;
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pit_irq_timer_update(s, s->count_load_time);
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}
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static void pit_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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{
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int channel, access;
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PITChannelState *s;
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addr &= 3;
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if (addr == 3) {
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channel = val >> 6;
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if (channel == 3)
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return;
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s = &pit_channels[channel];
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access = (val >> 4) & 3;
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switch(access) {
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case 0:
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s->latched_count = pit_get_count(s);
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s->rw_state = RW_STATE_LATCHED_WORD0;
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break;
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default:
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s->mode = (val >> 1) & 7;
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s->bcd = val & 1;
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s->rw_state = access - 1 + RW_STATE_LSB;
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/* XXX: update irq timer ? */
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break;
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}
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} else {
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s = &pit_channels[addr];
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switch(s->rw_state) {
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case RW_STATE_LSB:
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pit_load_count(s, val);
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break;
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case RW_STATE_MSB:
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pit_load_count(s, val << 8);
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break;
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case RW_STATE_WORD0:
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case RW_STATE_WORD1:
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if (s->rw_state & 1) {
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pit_load_count(s, (s->latched_count & 0xff) | (val << 8));
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} else {
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s->latched_count = val;
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}
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s->rw_state ^= 1;
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break;
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}
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}
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}
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static uint32_t pit_ioport_read(void *opaque, uint32_t addr)
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{
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int ret, count;
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PITChannelState *s;
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addr &= 3;
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s = &pit_channels[addr];
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switch(s->rw_state) {
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case RW_STATE_LSB:
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case RW_STATE_MSB:
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case RW_STATE_WORD0:
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case RW_STATE_WORD1:
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count = pit_get_count(s);
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if (s->rw_state & 1)
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ret = (count >> 8) & 0xff;
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else
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ret = count & 0xff;
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if (s->rw_state & 2)
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s->rw_state ^= 1;
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break;
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default:
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case RW_STATE_LATCHED_WORD0:
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case RW_STATE_LATCHED_WORD1:
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if (s->rw_state & 1)
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ret = s->latched_count >> 8;
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else
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ret = s->latched_count & 0xff;
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s->rw_state ^= 1;
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break;
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}
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return ret;
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}
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static void pit_irq_timer_update(PITChannelState *s, int64_t current_time)
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{
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int64_t expire_time;
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int irq_level;
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if (!s->irq_timer)
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return;
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expire_time = pit_get_next_transition_time(s, current_time);
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irq_level = pit_get_out(s, current_time);
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pic_set_irq(s->irq, irq_level);
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#ifdef DEBUG_PIT
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printf("irq_level=%d next_delay=%f\n",
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irq_level,
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(double)(expire_time - current_time) / ticks_per_sec);
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#endif
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s->next_transition_time = expire_time;
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if (expire_time != -1)
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qemu_mod_timer(s->irq_timer, expire_time);
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else
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qemu_del_timer(s->irq_timer);
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}
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static void pit_irq_timer(void *opaque)
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{
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PITChannelState *s = opaque;
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pit_irq_timer_update(s, s->next_transition_time);
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}
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static void pit_save(QEMUFile *f, void *opaque)
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{
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PITChannelState *s;
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int i;
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for(i = 0; i < 3; i++) {
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s = &pit_channels[i];
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qemu_put_be32s(f, &s->count);
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qemu_put_be16s(f, &s->latched_count);
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qemu_put_8s(f, &s->rw_state);
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qemu_put_8s(f, &s->mode);
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qemu_put_8s(f, &s->bcd);
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qemu_put_8s(f, &s->gate);
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qemu_put_be64s(f, &s->count_load_time);
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if (s->irq_timer) {
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qemu_put_be64s(f, &s->next_transition_time);
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qemu_put_timer(f, s->irq_timer);
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}
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}
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}
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static int pit_load(QEMUFile *f, void *opaque, int version_id)
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{
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PITChannelState *s;
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int i;
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if (version_id != 1)
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return -EINVAL;
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for(i = 0; i < 3; i++) {
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s = &pit_channels[i];
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qemu_get_be32s(f, &s->count);
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qemu_get_be16s(f, &s->latched_count);
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qemu_get_8s(f, &s->rw_state);
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qemu_get_8s(f, &s->mode);
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qemu_get_8s(f, &s->bcd);
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qemu_get_8s(f, &s->gate);
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qemu_get_be64s(f, &s->count_load_time);
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if (s->irq_timer) {
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qemu_get_be64s(f, &s->next_transition_time);
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qemu_get_timer(f, s->irq_timer);
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}
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}
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return 0;
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}
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void pit_init(int base, int irq)
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{
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PITChannelState *s;
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int i;
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for(i = 0;i < 3; i++) {
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s = &pit_channels[i];
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if (i == 0) {
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/* the timer 0 is connected to an IRQ */
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s->irq_timer = qemu_new_timer(vm_clock, pit_irq_timer, s);
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s->irq = irq;
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}
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s->mode = 3;
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s->gate = (i != 2);
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pit_load_count(s, 0);
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}
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register_savevm("i8254", base, 1, pit_save, pit_load, NULL);
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register_ioport_write(base, 4, 1, pit_ioport_write, NULL);
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register_ioport_read(base, 3, 1, pit_ioport_read, NULL);
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}
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