Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
751 lines
22 KiB
C
751 lines
22 KiB
C
/*
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* OneNAND flash memories emulation.
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*
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* Copyright (C) 2008 Nokia Corporation
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* Written by Andrzej Zaborowski <andrew@openedhand.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu-common.h"
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#include "hw.h"
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#include "flash.h"
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#include "irq.h"
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#include "blockdev.h"
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#include "memory.h"
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#include "exec-memory.h"
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/* 11 for 2kB-page OneNAND ("2nd generation") and 10 for 1kB-page chips */
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#define PAGE_SHIFT 11
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/* Fixed */
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#define BLOCK_SHIFT (PAGE_SHIFT + 6)
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typedef struct {
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struct {
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uint16_t man;
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uint16_t dev;
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uint16_t ver;
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} id;
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int shift;
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target_phys_addr_t base;
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qemu_irq intr;
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qemu_irq rdy;
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BlockDriverState *bdrv;
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BlockDriverState *bdrv_cur;
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uint8_t *image;
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uint8_t *otp;
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uint8_t *current;
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MemoryRegion ram;
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MemoryRegion mapped_ram;
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uint8_t *boot[2];
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uint8_t *data[2][2];
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MemoryRegion iomem;
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MemoryRegion container;
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int cycle;
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int otpmode;
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uint16_t addr[8];
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uint16_t unladdr[8];
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int bufaddr;
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int count;
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uint16_t command;
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uint16_t config[2];
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uint16_t status;
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uint16_t intstatus;
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uint16_t wpstatus;
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ECCState ecc;
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int density_mask;
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int secs;
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int secs_cur;
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int blocks;
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uint8_t *blockwp;
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} OneNANDState;
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enum {
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ONEN_BUF_BLOCK = 0,
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ONEN_BUF_BLOCK2 = 1,
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ONEN_BUF_DEST_BLOCK = 2,
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ONEN_BUF_DEST_PAGE = 3,
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ONEN_BUF_PAGE = 7,
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};
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enum {
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ONEN_ERR_CMD = 1 << 10,
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ONEN_ERR_ERASE = 1 << 11,
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ONEN_ERR_PROG = 1 << 12,
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ONEN_ERR_LOAD = 1 << 13,
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};
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enum {
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ONEN_INT_RESET = 1 << 4,
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ONEN_INT_ERASE = 1 << 5,
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ONEN_INT_PROG = 1 << 6,
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ONEN_INT_LOAD = 1 << 7,
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ONEN_INT = 1 << 15,
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};
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enum {
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ONEN_LOCK_LOCKTIGHTEN = 1 << 0,
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ONEN_LOCK_LOCKED = 1 << 1,
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ONEN_LOCK_UNLOCKED = 1 << 2,
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};
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static void onenand_mem_setup(OneNANDState *s)
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{
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/* XXX: We should use IO_MEM_ROMD but we broke it earlier...
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* Both 0x0000 ... 0x01ff and 0x8000 ... 0x800f can be used to
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* write boot commands. Also take note of the BWPS bit. */
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memory_region_init(&s->container, "onenand", 0x10000 << s->shift);
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memory_region_add_subregion(&s->container, 0, &s->iomem);
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memory_region_init_alias(&s->mapped_ram, "onenand-mapped-ram",
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&s->ram, 0x0200 << s->shift,
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0xbe00 << s->shift);
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memory_region_add_subregion_overlap(&s->container,
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0x0200 << s->shift,
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&s->mapped_ram,
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1);
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}
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void onenand_base_update(void *opaque, target_phys_addr_t new)
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{
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OneNANDState *s = (OneNANDState *) opaque;
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s->base = new;
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memory_region_add_subregion(get_system_memory(), s->base, &s->container);
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}
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void onenand_base_unmap(void *opaque)
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{
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OneNANDState *s = (OneNANDState *) opaque;
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memory_region_del_subregion(get_system_memory(), &s->container);
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}
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static void onenand_intr_update(OneNANDState *s)
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{
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qemu_set_irq(s->intr, ((s->intstatus >> 15) ^ (~s->config[0] >> 6)) & 1);
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}
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/* Hot reset (Reset OneNAND command) or warm reset (RP pin low) */
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static void onenand_reset(OneNANDState *s, int cold)
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{
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memset(&s->addr, 0, sizeof(s->addr));
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s->command = 0;
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s->count = 1;
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s->bufaddr = 0;
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s->config[0] = 0x40c0;
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s->config[1] = 0x0000;
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onenand_intr_update(s);
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qemu_irq_raise(s->rdy);
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s->status = 0x0000;
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s->intstatus = cold ? 0x8080 : 0x8010;
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s->unladdr[0] = 0;
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s->unladdr[1] = 0;
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s->wpstatus = 0x0002;
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s->cycle = 0;
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s->otpmode = 0;
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s->bdrv_cur = s->bdrv;
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s->current = s->image;
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s->secs_cur = s->secs;
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if (cold) {
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/* Lock the whole flash */
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memset(s->blockwp, ONEN_LOCK_LOCKED, s->blocks);
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if (s->bdrv && bdrv_read(s->bdrv, 0, s->boot[0], 8) < 0)
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hw_error("%s: Loading the BootRAM failed.\n", __FUNCTION__);
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}
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}
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static inline int onenand_load_main(OneNANDState *s, int sec, int secn,
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void *dest)
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{
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if (s->bdrv_cur)
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return bdrv_read(s->bdrv_cur, sec, dest, secn) < 0;
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else if (sec + secn > s->secs_cur)
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return 1;
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memcpy(dest, s->current + (sec << 9), secn << 9);
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return 0;
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}
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static inline int onenand_prog_main(OneNANDState *s, int sec, int secn,
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void *src)
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{
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int result = 0;
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if (secn > 0) {
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uint32_t size = (uint32_t) secn * 512;
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const uint8_t *sp = (const uint8_t *) src;
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uint8_t *dp = 0;
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if (s->bdrv_cur) {
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dp = g_malloc(size);
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if (!dp || bdrv_read(s->bdrv_cur, sec, dp, secn) < 0) {
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result = 1;
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}
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} else {
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if (sec + secn > s->secs_cur) {
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result = 1;
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} else {
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dp = (uint8_t *) s->current + (sec << 9);
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}
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}
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if (!result) {
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uint32_t i;
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for (i = 0; i < size; i++) {
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dp[i] &= sp[i];
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}
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if (s->bdrv_cur) {
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result = bdrv_write(s->bdrv_cur, sec, dp, secn) < 0;
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}
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}
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if (dp && s->bdrv_cur) {
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g_free(dp);
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}
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}
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return result;
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}
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static inline int onenand_load_spare(OneNANDState *s, int sec, int secn,
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void *dest)
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{
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uint8_t buf[512];
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if (s->bdrv_cur) {
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if (bdrv_read(s->bdrv_cur, s->secs_cur + (sec >> 5), buf, 1) < 0)
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return 1;
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memcpy(dest, buf + ((sec & 31) << 4), secn << 4);
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} else if (sec + secn > s->secs_cur)
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return 1;
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else
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memcpy(dest, s->current + (s->secs_cur << 9) + (sec << 4), secn << 4);
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return 0;
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}
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static inline int onenand_prog_spare(OneNANDState *s, int sec, int secn,
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void *src)
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{
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int result = 0;
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if (secn > 0) {
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const uint8_t *sp = (const uint8_t *) src;
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uint8_t *dp = 0, *dpp = 0;
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if (s->bdrv_cur) {
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dp = g_malloc(512);
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if (!dp || bdrv_read(s->bdrv_cur,
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s->secs_cur + (sec >> 5),
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dp, 1) < 0) {
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result = 1;
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} else {
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dpp = dp + ((sec & 31) << 4);
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}
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} else {
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if (sec + secn > s->secs_cur) {
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result = 1;
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} else {
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dpp = s->current + (s->secs_cur << 9) + (sec << 4);
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}
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}
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if (!result) {
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uint32_t i;
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for (i = 0; i < (secn << 4); i++) {
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dpp[i] &= sp[i];
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}
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if (s->bdrv_cur) {
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result = bdrv_write(s->bdrv_cur, s->secs_cur + (sec >> 5),
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dp, 1) < 0;
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}
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}
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if (dp) {
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g_free(dp);
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}
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}
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return result;
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}
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static inline int onenand_erase(OneNANDState *s, int sec, int num)
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{
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uint8_t *blankbuf, *tmpbuf;
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blankbuf = g_malloc(512);
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if (!blankbuf) {
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return 1;
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}
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tmpbuf = g_malloc(512);
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if (!tmpbuf) {
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g_free(blankbuf);
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return 1;
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}
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memset(blankbuf, 0xff, 512);
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for (; num > 0; num--, sec++) {
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if (s->bdrv_cur) {
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int erasesec = s->secs_cur + (sec >> 5);
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if (bdrv_write(s->bdrv_cur, sec, blankbuf, 1)) {
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goto fail;
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}
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if (bdrv_read(s->bdrv_cur, erasesec, tmpbuf, 1) < 0) {
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goto fail;
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}
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memcpy(tmpbuf + ((sec & 31) << 4), blankbuf, 1 << 4);
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if (bdrv_write(s->bdrv_cur, erasesec, tmpbuf, 1) < 0) {
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goto fail;
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}
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} else {
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if (sec + 1 > s->secs_cur) {
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goto fail;
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}
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memcpy(s->current + (sec << 9), blankbuf, 512);
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memcpy(s->current + (s->secs_cur << 9) + (sec << 4),
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blankbuf, 1 << 4);
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}
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}
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g_free(tmpbuf);
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g_free(blankbuf);
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return 0;
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fail:
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g_free(tmpbuf);
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g_free(blankbuf);
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return 1;
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}
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static void onenand_command(OneNANDState *s, int cmd)
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{
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int b;
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int sec;
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void *buf;
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#define SETADDR(block, page) \
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sec = (s->addr[page] & 3) + \
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((((s->addr[page] >> 2) & 0x3f) + \
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(((s->addr[block] & 0xfff) | \
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(s->addr[block] >> 15 ? \
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s->density_mask : 0)) << 6)) << (PAGE_SHIFT - 9));
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#define SETBUF_M() \
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buf = (s->bufaddr & 8) ? \
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s->data[(s->bufaddr >> 2) & 1][0] : s->boot[0]; \
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buf += (s->bufaddr & 3) << 9;
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#define SETBUF_S() \
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buf = (s->bufaddr & 8) ? \
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s->data[(s->bufaddr >> 2) & 1][1] : s->boot[1]; \
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buf += (s->bufaddr & 3) << 4;
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switch (cmd) {
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case 0x00: /* Load single/multiple sector data unit into buffer */
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SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE)
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SETBUF_M()
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if (onenand_load_main(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_LOAD;
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#if 0
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SETBUF_S()
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if (onenand_load_spare(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_LOAD;
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#endif
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/* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
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* or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
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* then we need two split the read/write into two chunks.
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*/
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s->intstatus |= ONEN_INT | ONEN_INT_LOAD;
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break;
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case 0x13: /* Load single/multiple spare sector into buffer */
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SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE)
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SETBUF_S()
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if (onenand_load_spare(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_LOAD;
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/* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
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* or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
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* then we need two split the read/write into two chunks.
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*/
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s->intstatus |= ONEN_INT | ONEN_INT_LOAD;
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break;
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case 0x80: /* Program single/multiple sector data unit from buffer */
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SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE)
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SETBUF_M()
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if (onenand_prog_main(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG;
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#if 0
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SETBUF_S()
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if (onenand_prog_spare(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG;
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#endif
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/* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
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* or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
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* then we need two split the read/write into two chunks.
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*/
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s->intstatus |= ONEN_INT | ONEN_INT_PROG;
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break;
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case 0x1a: /* Program single/multiple spare area sector from buffer */
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SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE)
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SETBUF_S()
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if (onenand_prog_spare(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG;
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/* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
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* or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
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* then we need two split the read/write into two chunks.
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*/
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s->intstatus |= ONEN_INT | ONEN_INT_PROG;
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break;
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case 0x1b: /* Copy-back program */
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SETBUF_S()
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SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE)
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if (onenand_load_main(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG;
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SETADDR(ONEN_BUF_DEST_BLOCK, ONEN_BUF_DEST_PAGE)
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if (onenand_prog_main(s, sec, s->count, buf))
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s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG;
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/* TODO: spare areas */
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s->intstatus |= ONEN_INT | ONEN_INT_PROG;
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break;
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case 0x23: /* Unlock NAND array block(s) */
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s->intstatus |= ONEN_INT;
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/* XXX the previous (?) area should be locked automatically */
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for (b = s->unladdr[0]; b <= s->unladdr[1]; b ++) {
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if (b >= s->blocks) {
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s->status |= ONEN_ERR_CMD;
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break;
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}
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if (s->blockwp[b] == ONEN_LOCK_LOCKTIGHTEN)
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break;
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s->wpstatus = s->blockwp[b] = ONEN_LOCK_UNLOCKED;
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}
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break;
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case 0x27: /* Unlock All NAND array blocks */
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s->intstatus |= ONEN_INT;
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for (b = 0; b < s->blocks; b ++) {
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if (b >= s->blocks) {
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s->status |= ONEN_ERR_CMD;
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break;
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}
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if (s->blockwp[b] == ONEN_LOCK_LOCKTIGHTEN)
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break;
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s->wpstatus = s->blockwp[b] = ONEN_LOCK_UNLOCKED;
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}
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break;
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case 0x2a: /* Lock NAND array block(s) */
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s->intstatus |= ONEN_INT;
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for (b = s->unladdr[0]; b <= s->unladdr[1]; b ++) {
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if (b >= s->blocks) {
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s->status |= ONEN_ERR_CMD;
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break;
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}
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if (s->blockwp[b] == ONEN_LOCK_LOCKTIGHTEN)
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break;
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s->wpstatus = s->blockwp[b] = ONEN_LOCK_LOCKED;
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}
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break;
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case 0x2c: /* Lock-tight NAND array block(s) */
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s->intstatus |= ONEN_INT;
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for (b = s->unladdr[0]; b <= s->unladdr[1]; b ++) {
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if (b >= s->blocks) {
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s->status |= ONEN_ERR_CMD;
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break;
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}
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if (s->blockwp[b] == ONEN_LOCK_UNLOCKED)
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continue;
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s->wpstatus = s->blockwp[b] = ONEN_LOCK_LOCKTIGHTEN;
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}
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break;
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case 0x71: /* Erase-Verify-Read */
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s->intstatus |= ONEN_INT;
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break;
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case 0x95: /* Multi-block erase */
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qemu_irq_pulse(s->intr);
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/* Fall through. */
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case 0x94: /* Block erase */
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sec = ((s->addr[ONEN_BUF_BLOCK] & 0xfff) |
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(s->addr[ONEN_BUF_BLOCK] >> 15 ? s->density_mask : 0))
|
|
<< (BLOCK_SHIFT - 9);
|
|
if (onenand_erase(s, sec, 1 << (BLOCK_SHIFT - 9)))
|
|
s->status |= ONEN_ERR_CMD | ONEN_ERR_ERASE;
|
|
|
|
s->intstatus |= ONEN_INT | ONEN_INT_ERASE;
|
|
break;
|
|
case 0xb0: /* Erase suspend */
|
|
break;
|
|
case 0x30: /* Erase resume */
|
|
s->intstatus |= ONEN_INT | ONEN_INT_ERASE;
|
|
break;
|
|
|
|
case 0xf0: /* Reset NAND Flash core */
|
|
onenand_reset(s, 0);
|
|
break;
|
|
case 0xf3: /* Reset OneNAND */
|
|
onenand_reset(s, 0);
|
|
break;
|
|
|
|
case 0x65: /* OTP Access */
|
|
s->intstatus |= ONEN_INT;
|
|
s->bdrv_cur = NULL;
|
|
s->current = s->otp;
|
|
s->secs_cur = 1 << (BLOCK_SHIFT - 9);
|
|
s->addr[ONEN_BUF_BLOCK] = 0;
|
|
s->otpmode = 1;
|
|
break;
|
|
|
|
default:
|
|
s->status |= ONEN_ERR_CMD;
|
|
s->intstatus |= ONEN_INT;
|
|
fprintf(stderr, "%s: unknown OneNAND command %x\n",
|
|
__FUNCTION__, cmd);
|
|
}
|
|
|
|
onenand_intr_update(s);
|
|
}
|
|
|
|
static uint64_t onenand_read(void *opaque, target_phys_addr_t addr,
|
|
unsigned size)
|
|
{
|
|
OneNANDState *s = (OneNANDState *) opaque;
|
|
int offset = addr >> s->shift;
|
|
|
|
switch (offset) {
|
|
case 0x0000 ... 0xc000:
|
|
return lduw_le_p(s->boot[0] + addr);
|
|
|
|
case 0xf000: /* Manufacturer ID */
|
|
return s->id.man;
|
|
case 0xf001: /* Device ID */
|
|
return s->id.dev;
|
|
case 0xf002: /* Version ID */
|
|
return s->id.ver;
|
|
/* TODO: get the following values from a real chip! */
|
|
case 0xf003: /* Data Buffer size */
|
|
return 1 << PAGE_SHIFT;
|
|
case 0xf004: /* Boot Buffer size */
|
|
return 0x200;
|
|
case 0xf005: /* Amount of buffers */
|
|
return 1 | (2 << 8);
|
|
case 0xf006: /* Technology */
|
|
return 0;
|
|
|
|
case 0xf100 ... 0xf107: /* Start addresses */
|
|
return s->addr[offset - 0xf100];
|
|
|
|
case 0xf200: /* Start buffer */
|
|
return (s->bufaddr << 8) | ((s->count - 1) & (1 << (PAGE_SHIFT - 10)));
|
|
|
|
case 0xf220: /* Command */
|
|
return s->command;
|
|
case 0xf221: /* System Configuration 1 */
|
|
return s->config[0] & 0xffe0;
|
|
case 0xf222: /* System Configuration 2 */
|
|
return s->config[1];
|
|
|
|
case 0xf240: /* Controller Status */
|
|
return s->status;
|
|
case 0xf241: /* Interrupt */
|
|
return s->intstatus;
|
|
case 0xf24c: /* Unlock Start Block Address */
|
|
return s->unladdr[0];
|
|
case 0xf24d: /* Unlock End Block Address */
|
|
return s->unladdr[1];
|
|
case 0xf24e: /* Write Protection Status */
|
|
return s->wpstatus;
|
|
|
|
case 0xff00: /* ECC Status */
|
|
return 0x00;
|
|
case 0xff01: /* ECC Result of main area data */
|
|
case 0xff02: /* ECC Result of spare area data */
|
|
case 0xff03: /* ECC Result of main area data */
|
|
case 0xff04: /* ECC Result of spare area data */
|
|
hw_error("%s: imeplement ECC\n", __FUNCTION__);
|
|
return 0x0000;
|
|
}
|
|
|
|
fprintf(stderr, "%s: unknown OneNAND register %x\n",
|
|
__FUNCTION__, offset);
|
|
return 0;
|
|
}
|
|
|
|
static void onenand_write(void *opaque, target_phys_addr_t addr,
|
|
uint64_t value, unsigned size)
|
|
{
|
|
OneNANDState *s = (OneNANDState *) opaque;
|
|
int offset = addr >> s->shift;
|
|
int sec;
|
|
|
|
switch (offset) {
|
|
case 0x0000 ... 0x01ff:
|
|
case 0x8000 ... 0x800f:
|
|
if (s->cycle) {
|
|
s->cycle = 0;
|
|
|
|
if (value == 0x0000) {
|
|
SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE)
|
|
onenand_load_main(s, sec,
|
|
1 << (PAGE_SHIFT - 9), s->data[0][0]);
|
|
s->addr[ONEN_BUF_PAGE] += 4;
|
|
s->addr[ONEN_BUF_PAGE] &= 0xff;
|
|
}
|
|
break;
|
|
}
|
|
|
|
switch (value) {
|
|
case 0x00f0: /* Reset OneNAND */
|
|
onenand_reset(s, 0);
|
|
break;
|
|
|
|
case 0x00e0: /* Load Data into Buffer */
|
|
s->cycle = 1;
|
|
break;
|
|
|
|
case 0x0090: /* Read Identification Data */
|
|
memset(s->boot[0], 0, 3 << s->shift);
|
|
s->boot[0][0 << s->shift] = s->id.man & 0xff;
|
|
s->boot[0][1 << s->shift] = s->id.dev & 0xff;
|
|
s->boot[0][2 << s->shift] = s->wpstatus & 0xff;
|
|
break;
|
|
|
|
default:
|
|
fprintf(stderr, "%s: unknown OneNAND boot command %"PRIx64"\n",
|
|
__FUNCTION__, value);
|
|
}
|
|
break;
|
|
|
|
case 0xf100 ... 0xf107: /* Start addresses */
|
|
s->addr[offset - 0xf100] = value;
|
|
break;
|
|
|
|
case 0xf200: /* Start buffer */
|
|
s->bufaddr = (value >> 8) & 0xf;
|
|
if (PAGE_SHIFT == 11)
|
|
s->count = (value & 3) ?: 4;
|
|
else if (PAGE_SHIFT == 10)
|
|
s->count = (value & 1) ?: 2;
|
|
break;
|
|
|
|
case 0xf220: /* Command */
|
|
if (s->intstatus & (1 << 15))
|
|
break;
|
|
s->command = value;
|
|
onenand_command(s, s->command);
|
|
break;
|
|
case 0xf221: /* System Configuration 1 */
|
|
s->config[0] = value;
|
|
onenand_intr_update(s);
|
|
qemu_set_irq(s->rdy, (s->config[0] >> 7) & 1);
|
|
break;
|
|
case 0xf222: /* System Configuration 2 */
|
|
s->config[1] = value;
|
|
break;
|
|
|
|
case 0xf241: /* Interrupt */
|
|
s->intstatus &= value;
|
|
if ((1 << 15) & ~s->intstatus)
|
|
s->status &= ~(ONEN_ERR_CMD | ONEN_ERR_ERASE |
|
|
ONEN_ERR_PROG | ONEN_ERR_LOAD);
|
|
onenand_intr_update(s);
|
|
break;
|
|
case 0xf24c: /* Unlock Start Block Address */
|
|
s->unladdr[0] = value & (s->blocks - 1);
|
|
/* For some reason we have to set the end address to by default
|
|
* be same as start because the software forgets to write anything
|
|
* in there. */
|
|
s->unladdr[1] = value & (s->blocks - 1);
|
|
break;
|
|
case 0xf24d: /* Unlock End Block Address */
|
|
s->unladdr[1] = value & (s->blocks - 1);
|
|
break;
|
|
|
|
default:
|
|
fprintf(stderr, "%s: unknown OneNAND register %x\n",
|
|
__FUNCTION__, offset);
|
|
}
|
|
}
|
|
|
|
static const MemoryRegionOps onenand_ops = {
|
|
.read = onenand_read,
|
|
.write = onenand_write,
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
};
|
|
|
|
void *onenand_init(BlockDriverState *bdrv,
|
|
uint16_t man_id, uint16_t dev_id, uint16_t ver_id,
|
|
int regshift, qemu_irq irq)
|
|
{
|
|
OneNANDState *s = (OneNANDState *) g_malloc0(sizeof(*s));
|
|
uint32_t size = 1 << (24 + ((dev_id >> 4) & 7));
|
|
void *ram;
|
|
|
|
s->shift = regshift;
|
|
s->intr = irq;
|
|
s->rdy = NULL;
|
|
s->id.man = man_id;
|
|
s->id.dev = dev_id;
|
|
s->id.ver = ver_id;
|
|
s->blocks = size >> BLOCK_SHIFT;
|
|
s->secs = size >> 9;
|
|
s->blockwp = g_malloc(s->blocks);
|
|
s->density_mask = (dev_id & 0x08) ? (1 << (6 + ((dev_id >> 4) & 7))) : 0;
|
|
memory_region_init_io(&s->iomem, &onenand_ops, s, "onenand",
|
|
0x10000 << s->shift);
|
|
s->bdrv = bdrv;
|
|
if (!s->bdrv) {
|
|
s->image = memset(g_malloc(size + (size >> 5)),
|
|
0xff, size + (size >> 5));
|
|
}
|
|
s->otp = memset(g_malloc((64 + 2) << PAGE_SHIFT),
|
|
0xff, (64 + 2) << PAGE_SHIFT);
|
|
memory_region_init_ram(&s->ram, NULL, "onenand.ram", 0xc000 << s->shift);
|
|
ram = memory_region_get_ram_ptr(&s->ram);
|
|
s->boot[0] = ram + (0x0000 << s->shift);
|
|
s->boot[1] = ram + (0x8000 << s->shift);
|
|
s->data[0][0] = ram + ((0x0200 + (0 << (PAGE_SHIFT - 1))) << s->shift);
|
|
s->data[0][1] = ram + ((0x8010 + (0 << (PAGE_SHIFT - 6))) << s->shift);
|
|
s->data[1][0] = ram + ((0x0200 + (1 << (PAGE_SHIFT - 1))) << s->shift);
|
|
s->data[1][1] = ram + ((0x8010 + (1 << (PAGE_SHIFT - 6))) << s->shift);
|
|
onenand_mem_setup(s);
|
|
|
|
onenand_reset(s, 1);
|
|
|
|
return s;
|
|
}
|
|
|
|
void *onenand_raw_otp(void *opaque)
|
|
{
|
|
OneNANDState *s = (OneNANDState *) opaque;
|
|
|
|
return s->otp;
|
|
}
|