This was done in a mostly automated fashion. I did it in three steps and then rebased it into a single step which avoids repeatedly touching every file in the tree. The first step was a sed-based addition of the parent type to the subclass registration functions. The second step was another sed-based removal of subclass registration functions while also adding virtual functions from the base class into a class_init function as appropriate. Finally, a python script was used to convert the DeviceInfo structures and qdev_register_subclass functions to TypeInfo structures, class_init functions, and type_register_static calls. We are almost fully converted to QOM after this commit. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
170 lines
4.9 KiB
C
170 lines
4.9 KiB
C
/*
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* QEMU AMD PC-Net II (Am79C970A) emulation
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*
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* Copyright (c) 2004 Antony T Curtis
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/* This software was written to be compatible with the specification:
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* AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet
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* AMD Publication# 19436 Rev:E Amendment/0 Issue Date: June 2000
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*/
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/*
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* On Sparc32, this is the Lance (Am7990) part of chip STP2000 (Master I/O), also
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* produced as NCR89C100. See
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* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
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* and
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* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR92C990.txt
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*/
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#include "sysbus.h"
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#include "net.h"
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#include "qemu-timer.h"
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#include "qemu_socket.h"
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#include "sun4m.h"
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#include "pcnet.h"
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#include "trace.h"
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typedef struct {
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SysBusDevice busdev;
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PCNetState state;
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} SysBusPCNetState;
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static void parent_lance_reset(void *opaque, int irq, int level)
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{
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SysBusPCNetState *d = opaque;
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if (level)
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pcnet_h_reset(&d->state);
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}
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static void lance_mem_write(void *opaque, target_phys_addr_t addr,
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uint64_t val, unsigned size)
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{
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SysBusPCNetState *d = opaque;
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trace_lance_mem_writew(addr, val & 0xffff);
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pcnet_ioport_writew(&d->state, addr, val & 0xffff);
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}
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static uint64_t lance_mem_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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SysBusPCNetState *d = opaque;
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uint32_t val;
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val = pcnet_ioport_readw(&d->state, addr);
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trace_lance_mem_readw(addr, val & 0xffff);
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return val & 0xffff;
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}
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static const MemoryRegionOps lance_mem_ops = {
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.read = lance_mem_read,
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.write = lance_mem_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 2,
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.max_access_size = 2,
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},
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};
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static void lance_cleanup(VLANClientState *nc)
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{
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PCNetState *d = DO_UPCAST(NICState, nc, nc)->opaque;
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pcnet_common_cleanup(d);
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}
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static NetClientInfo net_lance_info = {
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.type = NET_CLIENT_TYPE_NIC,
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.size = sizeof(NICState),
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.can_receive = pcnet_can_receive,
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.receive = pcnet_receive,
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.link_status_changed = pcnet_set_link_status,
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.cleanup = lance_cleanup,
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};
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static const VMStateDescription vmstate_lance = {
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.name = "pcnet",
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.version_id = 3,
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.minimum_version_id = 2,
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.minimum_version_id_old = 2,
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.fields = (VMStateField []) {
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VMSTATE_STRUCT(state, SysBusPCNetState, 0, vmstate_pcnet, PCNetState),
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VMSTATE_END_OF_LIST()
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}
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};
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static int lance_init(SysBusDevice *dev)
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{
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SysBusPCNetState *d = FROM_SYSBUS(SysBusPCNetState, dev);
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PCNetState *s = &d->state;
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memory_region_init_io(&s->mmio, &lance_mem_ops, d, "lance-mmio", 4);
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qdev_init_gpio_in(&dev->qdev, parent_lance_reset, 1);
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sysbus_init_mmio(dev, &s->mmio);
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sysbus_init_irq(dev, &s->irq);
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s->phys_mem_read = ledma_memory_read;
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s->phys_mem_write = ledma_memory_write;
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return pcnet_common_init(&dev->qdev, s, &net_lance_info);
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}
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static void lance_reset(DeviceState *dev)
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{
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SysBusPCNetState *d = DO_UPCAST(SysBusPCNetState, busdev.qdev, dev);
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pcnet_h_reset(&d->state);
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}
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static Property lance_properties[] = {
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DEFINE_PROP_PTR("dma", SysBusPCNetState, state.dma_opaque),
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DEFINE_NIC_PROPERTIES(SysBusPCNetState, state.conf),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void lance_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
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k->init = lance_init;
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dc->fw_name = "ethernet";
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dc->reset = lance_reset;
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dc->vmsd = &vmstate_lance;
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dc->props = lance_properties;
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}
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static TypeInfo lance_info = {
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.name = "lance",
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(SysBusPCNetState),
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.class_init = lance_class_init,
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};
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static void lance_register_devices(void)
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{
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type_register_static(&lance_info);
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}
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device_init(lance_register_devices)
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