This was done in a mostly automated fashion. I did it in three steps and then rebased it into a single step which avoids repeatedly touching every file in the tree. The first step was a sed-based addition of the parent type to the subclass registration functions. The second step was another sed-based removal of subclass registration functions while also adding virtual functions from the base class into a class_init function as appropriate. Finally, a python script was used to convert the DeviceInfo structures and qdev_register_subclass functions to TypeInfo structures, class_init functions, and type_register_static calls. We are almost fully converted to QOM after this commit. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
173 lines
4.6 KiB
C
173 lines
4.6 KiB
C
/*
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* QEMU model of the LatticeMico32 system control block.
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*
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* Copyright (c) 2010 Michael Walle <michael@walle.cc>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* This model is mainly intended for testing purposes and doesn't fit to any
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* real hardware. On the one hand it provides a control register (R_CTRL) on
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* the other hand it supports the lm32 tests.
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*
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* A write to the control register causes a system shutdown.
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* Tests first write the pointer to a test name to the test name register
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* (R_TESTNAME) and then write a zero to the pass/fail register (R_PASSFAIL) if
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* the test is passed or any non-zero value to it if the test is failed.
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*/
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#include "hw.h"
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#include "sysbus.h"
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#include "trace.h"
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#include "qemu-log.h"
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#include "qemu-error.h"
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#include "sysemu.h"
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#include "qemu-log.h"
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enum {
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R_CTRL = 0,
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R_PASSFAIL,
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R_TESTNAME,
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R_MAX
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};
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#define MAX_TESTNAME_LEN 16
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struct LM32SysState {
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SysBusDevice busdev;
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MemoryRegion iomem;
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uint32_t base;
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uint32_t regs[R_MAX];
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uint8_t testname[MAX_TESTNAME_LEN];
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};
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typedef struct LM32SysState LM32SysState;
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static void copy_testname(LM32SysState *s)
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{
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cpu_physical_memory_read(s->regs[R_TESTNAME], s->testname,
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MAX_TESTNAME_LEN);
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s->testname[MAX_TESTNAME_LEN - 1] = '\0';
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}
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static void sys_write(void *opaque, target_phys_addr_t addr,
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uint64_t value, unsigned size)
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{
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LM32SysState *s = opaque;
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char *testname;
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trace_lm32_sys_memory_write(addr, value);
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addr >>= 2;
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switch (addr) {
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case R_CTRL:
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qemu_system_shutdown_request();
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break;
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case R_PASSFAIL:
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s->regs[addr] = value;
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testname = (char *)s->testname;
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qemu_log("TC %-16s %s\n", testname, (value) ? "FAILED" : "OK");
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break;
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case R_TESTNAME:
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s->regs[addr] = value;
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copy_testname(s);
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break;
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default:
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error_report("lm32_sys: write access to unknown register 0x"
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TARGET_FMT_plx, addr << 2);
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break;
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}
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}
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static bool sys_ops_accepts(void *opaque, target_phys_addr_t addr,
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unsigned size, bool is_write)
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{
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return is_write && size == 4;
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}
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static const MemoryRegionOps sys_ops = {
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.write = sys_write,
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.valid.accepts = sys_ops_accepts,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void sys_reset(DeviceState *d)
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{
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LM32SysState *s = container_of(d, LM32SysState, busdev.qdev);
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int i;
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for (i = 0; i < R_MAX; i++) {
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s->regs[i] = 0;
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}
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memset(s->testname, 0, MAX_TESTNAME_LEN);
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}
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static int lm32_sys_init(SysBusDevice *dev)
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{
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LM32SysState *s = FROM_SYSBUS(typeof(*s), dev);
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memory_region_init_io(&s->iomem, &sys_ops , s, "sys", R_MAX * 4);
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sysbus_init_mmio(dev, &s->iomem);
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/* Note: This device is not created in the board initialization,
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* instead it has to be added with the -device parameter. Therefore,
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* the device maps itself. */
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sysbus_mmio_map(dev, 0, s->base);
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return 0;
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}
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static const VMStateDescription vmstate_lm32_sys = {
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.name = "lm32-sys",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, LM32SysState, R_MAX),
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VMSTATE_BUFFER(testname, LM32SysState),
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VMSTATE_END_OF_LIST()
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}
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};
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static Property lm32_sys_properties[] = {
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DEFINE_PROP_UINT32("base", LM32SysState, base, 0xffff0000),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void lm32_sys_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
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k->init = lm32_sys_init;
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dc->reset = sys_reset;
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dc->vmsd = &vmstate_lm32_sys;
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dc->props = lm32_sys_properties;
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}
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static TypeInfo lm32_sys_info = {
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.name = "lm32-sys",
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(LM32SysState),
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.class_init = lm32_sys_class_init,
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};
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static void lm32_sys_register(void)
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{
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type_register_static(&lm32_sys_info);
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}
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device_init(lm32_sys_register)
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