Move pci bridge related code into pci_bridge.c from pci.c for further enhancement. pci.c is big enough now, so split it out. No code change but exporting some accesser functions. In fact, few pci bridge functions stays in pci.c. Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
395 lines
12 KiB
C
395 lines
12 KiB
C
#ifndef QEMU_PCI_H
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#define QEMU_PCI_H
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#include "qemu-common.h"
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#include "qobject.h"
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#include "qdev.h"
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/* PCI includes legacy ISA access. */
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#include "isa.h"
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/* PCI bus */
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#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
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#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
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#define PCI_FUNC(devfn) ((devfn) & 0x07)
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#define PCI_FUNC_MAX 8
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/* Class, Vendor and Device IDs from Linux's pci_ids.h */
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#include "pci_ids.h"
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/* QEMU-specific Vendor and Device ID definitions */
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/* IBM (0x1014) */
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#define PCI_DEVICE_ID_IBM_440GX 0x027f
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#define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff
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/* Hitachi (0x1054) */
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#define PCI_VENDOR_ID_HITACHI 0x1054
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#define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e
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/* Apple (0x106b) */
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#define PCI_DEVICE_ID_APPLE_343S1201 0x0010
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#define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e
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#define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f
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#define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022
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#define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f
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/* Realtek (0x10ec) */
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#define PCI_DEVICE_ID_REALTEK_8029 0x8029
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/* Xilinx (0x10ee) */
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#define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300
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/* Marvell (0x11ab) */
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#define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620
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/* QEMU/Bochs VGA (0x1234) */
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#define PCI_VENDOR_ID_QEMU 0x1234
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#define PCI_DEVICE_ID_QEMU_VGA 0x1111
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/* VMWare (0x15ad) */
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#define PCI_VENDOR_ID_VMWARE 0x15ad
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#define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
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#define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
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#define PCI_DEVICE_ID_VMWARE_NET 0x0720
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#define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
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#define PCI_DEVICE_ID_VMWARE_IDE 0x1729
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/* Intel (0x8086) */
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#define PCI_DEVICE_ID_INTEL_82551IT 0x1209
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#define PCI_DEVICE_ID_INTEL_82557 0x1229
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/* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
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#define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
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#define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
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#define PCI_SUBDEVICE_ID_QEMU 0x1100
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#define PCI_DEVICE_ID_VIRTIO_NET 0x1000
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#define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001
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#define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
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#define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
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#define FMT_PCIBUS PRIx64
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typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
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uint32_t address, uint32_t data, int len);
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typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
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uint32_t address, int len);
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typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
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pcibus_t addr, pcibus_t size, int type);
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typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
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typedef struct PCIIORegion {
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pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
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#define PCI_BAR_UNMAPPED (~(pcibus_t)0)
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pcibus_t size;
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pcibus_t filtered_size;
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uint8_t type;
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PCIMapIORegionFunc *map_func;
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} PCIIORegion;
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#define PCI_ROM_SLOT 6
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#define PCI_NUM_REGIONS 7
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#include "pci_regs.h"
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/* PCI HEADER_TYPE */
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#define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
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/* Size of the standard PCI config header */
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#define PCI_CONFIG_HEADER_SIZE 0x40
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/* Size of the standard PCI config space */
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#define PCI_CONFIG_SPACE_SIZE 0x100
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/* Size of the standart PCIe config space: 4KB */
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#define PCIE_CONFIG_SPACE_SIZE 0x1000
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#define PCI_NUM_PINS 4 /* A-D */
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/* Bits in cap_present field. */
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enum {
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QEMU_PCI_CAP_MSIX = 0x1,
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QEMU_PCI_CAP_EXPRESS = 0x2,
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/* multifunction capable device */
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#define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 2
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QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
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};
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struct PCIDevice {
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DeviceState qdev;
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/* PCI config space */
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uint8_t *config;
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/* Used to enable config checks on load. Note that writeable bits are
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* never checked even if set in cmask. */
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uint8_t *cmask;
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/* Used to implement R/W bytes */
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uint8_t *wmask;
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/* Used to allocate config space for capabilities. */
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uint8_t *used;
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/* the following fields are read only */
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PCIBus *bus;
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uint32_t devfn;
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char name[64];
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PCIIORegion io_regions[PCI_NUM_REGIONS];
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/* do not access the following fields */
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PCIConfigReadFunc *config_read;
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PCIConfigWriteFunc *config_write;
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/* IRQ objects for the INTA-INTD pins. */
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qemu_irq *irq;
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/* Current IRQ levels. Used internally by the generic PCI code. */
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uint8_t irq_state;
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/* Capability bits */
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uint32_t cap_present;
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/* Offset of MSI-X capability in config space */
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uint8_t msix_cap;
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/* MSI-X entries */
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int msix_entries_nr;
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/* Space to store MSIX table */
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uint8_t *msix_table_page;
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/* MMIO index used to map MSIX table and pending bit entries. */
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int msix_mmio_index;
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/* Reference-count for entries actually in use by driver. */
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unsigned *msix_entry_used;
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/* Region including the MSI-X table */
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uint32_t msix_bar_size;
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/* Version id needed for VMState */
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int32_t version_id;
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/* Location of option rom */
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char *romfile;
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ram_addr_t rom_offset;
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uint32_t rom_bar;
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};
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PCIDevice *pci_register_device(PCIBus *bus, const char *name,
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int instance_size, int devfn,
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PCIConfigReadFunc *config_read,
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PCIConfigWriteFunc *config_write);
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void pci_register_bar(PCIDevice *pci_dev, int region_num,
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pcibus_t size, int type,
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PCIMapIORegionFunc *map_func);
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int pci_add_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
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int pci_add_capability_at_offset(PCIDevice *pci_dev, uint8_t cap_id,
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uint8_t cap_offset, uint8_t cap_size);
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void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
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void pci_reserve_capability(PCIDevice *pci_dev, uint8_t offset, uint8_t size);
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uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
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uint32_t pci_default_read_config(PCIDevice *d,
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uint32_t address, int len);
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void pci_default_write_config(PCIDevice *d,
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uint32_t address, uint32_t val, int len);
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void pci_device_save(PCIDevice *s, QEMUFile *f);
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int pci_device_load(PCIDevice *s, QEMUFile *f);
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typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
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typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
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typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev, int state);
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void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
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const char *name, int devfn_min);
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PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min);
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void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
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void *irq_opaque, int nirq);
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void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
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PCIBus *pci_register_bus(DeviceState *parent, const char *name,
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pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
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void *irq_opaque, int devfn_min, int nirq);
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void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base);
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PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
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const char *default_devaddr);
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PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
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const char *default_devaddr);
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int pci_bus_num(PCIBus *s);
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void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d));
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PCIBus *pci_find_root_bus(int domain);
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int pci_find_domain(const PCIBus *bus);
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PCIBus *pci_find_bus(PCIBus *bus, int bus_num);
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PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function);
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PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
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int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
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unsigned *slotp);
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void do_pci_info_print(Monitor *mon, const QObject *data);
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void do_pci_info(Monitor *mon, QObject **ret_data);
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void pci_bridge_update_mappings(PCIBus *b);
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static inline void
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pci_set_byte(uint8_t *config, uint8_t val)
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{
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*config = val;
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}
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static inline uint8_t
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pci_get_byte(const uint8_t *config)
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{
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return *config;
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}
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static inline void
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pci_set_word(uint8_t *config, uint16_t val)
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{
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cpu_to_le16wu((uint16_t *)config, val);
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}
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static inline uint16_t
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pci_get_word(const uint8_t *config)
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{
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return le16_to_cpupu((const uint16_t *)config);
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}
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static inline void
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pci_set_long(uint8_t *config, uint32_t val)
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{
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cpu_to_le32wu((uint32_t *)config, val);
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}
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static inline uint32_t
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pci_get_long(const uint8_t *config)
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{
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return le32_to_cpupu((const uint32_t *)config);
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}
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static inline void
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pci_set_quad(uint8_t *config, uint64_t val)
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{
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cpu_to_le64w((uint64_t *)config, val);
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}
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static inline uint64_t
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pci_get_quad(const uint8_t *config)
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{
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return le64_to_cpup((const uint64_t *)config);
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}
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static inline void
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pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
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{
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pci_set_word(&pci_config[PCI_VENDOR_ID], val);
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}
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static inline void
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pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
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{
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pci_set_word(&pci_config[PCI_DEVICE_ID], val);
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}
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static inline void
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pci_config_set_revision(uint8_t *pci_config, uint8_t val)
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{
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pci_set_byte(&pci_config[PCI_REVISION_ID], val);
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}
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static inline void
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pci_config_set_class(uint8_t *pci_config, uint16_t val)
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{
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pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
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}
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static inline void
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pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
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{
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pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
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}
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static inline void
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pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
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{
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pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
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}
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typedef int (*pci_qdev_initfn)(PCIDevice *dev);
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typedef struct {
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DeviceInfo qdev;
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pci_qdev_initfn init;
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PCIUnregisterFunc *exit;
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PCIConfigReadFunc *config_read;
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PCIConfigWriteFunc *config_write;
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/*
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* pci-to-pci bridge or normal device.
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* This doesn't mean pci host switch.
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* When card bus bridge is supported, this would be enhanced.
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*/
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int is_bridge;
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/* pcie stuff */
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int is_express; /* is this device pci express? */
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/* rom bar */
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const char *romfile;
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} PCIDeviceInfo;
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void pci_qdev_register(PCIDeviceInfo *info);
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void pci_qdev_register_many(PCIDeviceInfo *info);
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PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
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const char *name);
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PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
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bool multifunction,
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const char *name);
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PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
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PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
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static inline int pci_is_express(const PCIDevice *d)
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{
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return d->cap_present & QEMU_PCI_CAP_EXPRESS;
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}
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static inline uint32_t pci_config_size(const PCIDevice *d)
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{
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return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
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}
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/* These are not pci specific. Should move into a separate header.
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* Only pci.c uses them, so keep them here for now.
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*/
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/* Get last byte of a range from offset + length.
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* Undefined for ranges that wrap around 0. */
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static inline uint64_t range_get_last(uint64_t offset, uint64_t len)
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{
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return offset + len - 1;
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}
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/* Check whether a given range covers a given byte. */
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static inline int range_covers_byte(uint64_t offset, uint64_t len,
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uint64_t byte)
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{
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return offset <= byte && byte <= range_get_last(offset, len);
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}
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/* Check whether 2 given ranges overlap.
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* Undefined if ranges that wrap around 0. */
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static inline int ranges_overlap(uint64_t first1, uint64_t len1,
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uint64_t first2, uint64_t len2)
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{
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uint64_t last1 = range_get_last(first1, len1);
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uint64_t last2 = range_get_last(first2, len2);
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return !(last2 < first1 || last1 < first2);
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}
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#endif
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