Transfer the state information for the SMBus registers and internal data so it will work on a VM transfer. Signed-off-by: Corey Minyard <cminyard@mvista.com> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
498 lines
14 KiB
C
498 lines
14 KiB
C
/*
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* PC SMBus implementation
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* splitted from acpi.c
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License version 2 as published by the Free Software Foundation.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "hw/boards.h"
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#include "hw/i2c/pm_smbus.h"
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#include "hw/i2c/smbus_master.h"
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#define SMBHSTSTS 0x00
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#define SMBHSTCNT 0x02
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#define SMBHSTCMD 0x03
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#define SMBHSTADD 0x04
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#define SMBHSTDAT0 0x05
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#define SMBHSTDAT1 0x06
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#define SMBBLKDAT 0x07
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#define SMBAUXCTL 0x0d
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#define STS_HOST_BUSY (1 << 0)
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#define STS_INTR (1 << 1)
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#define STS_DEV_ERR (1 << 2)
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#define STS_BUS_ERR (1 << 3)
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#define STS_FAILED (1 << 4)
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#define STS_SMBALERT (1 << 5)
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#define STS_INUSE_STS (1 << 6)
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#define STS_BYTE_DONE (1 << 7)
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/* Signs of successfully transaction end :
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* ByteDoneStatus = 1 (STS_BYTE_DONE) and INTR = 1 (STS_INTR )
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*/
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#define CTL_INTREN (1 << 0)
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#define CTL_KILL (1 << 1)
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#define CTL_LAST_BYTE (1 << 5)
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#define CTL_START (1 << 6)
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#define CTL_PEC_EN (1 << 7)
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#define CTL_RETURN_MASK 0x1f
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#define PROT_QUICK 0
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#define PROT_BYTE 1
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#define PROT_BYTE_DATA 2
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#define PROT_WORD_DATA 3
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#define PROT_PROC_CALL 4
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#define PROT_BLOCK_DATA 5
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#define PROT_I2C_BLOCK_READ 6
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#define AUX_PEC (1 << 0)
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#define AUX_BLK (1 << 1)
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#define AUX_MASK 0x3
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/*#define DEBUG*/
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#ifdef DEBUG
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# define SMBUS_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
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#else
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# define SMBUS_DPRINTF(format, ...) do { } while (0)
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#endif
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static void smb_transaction(PMSMBus *s)
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{
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uint8_t prot = (s->smb_ctl >> 2) & 0x07;
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uint8_t read = s->smb_addr & 0x01;
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uint8_t cmd = s->smb_cmd;
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uint8_t addr = s->smb_addr >> 1;
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I2CBus *bus = s->smbus;
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int ret;
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SMBUS_DPRINTF("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
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/* Transaction isn't exec if STS_DEV_ERR bit set */
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if ((s->smb_stat & STS_DEV_ERR) != 0) {
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goto error;
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}
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switch(prot) {
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case PROT_QUICK:
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ret = smbus_quick_command(bus, addr, read);
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goto done;
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case PROT_BYTE:
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if (read) {
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ret = smbus_receive_byte(bus, addr);
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goto data8;
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} else {
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ret = smbus_send_byte(bus, addr, cmd);
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goto done;
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}
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case PROT_BYTE_DATA:
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if (read) {
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ret = smbus_read_byte(bus, addr, cmd);
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goto data8;
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} else {
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ret = smbus_write_byte(bus, addr, cmd, s->smb_data0);
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goto done;
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}
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break;
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case PROT_WORD_DATA:
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if (read) {
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ret = smbus_read_word(bus, addr, cmd);
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goto data16;
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} else {
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ret = smbus_write_word(bus, addr, cmd,
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(s->smb_data1 << 8) | s->smb_data0);
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goto done;
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}
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break;
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case PROT_I2C_BLOCK_READ:
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/* According to the Linux i2c-i801 driver:
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* NB: page 240 of ICH5 datasheet shows that the R/#W
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* bit should be cleared here, even when reading.
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* However if SPD Write Disable is set (Lynx Point and later),
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* the read will fail if we don't set the R/#W bit.
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* So at least Linux may or may not set the read bit here.
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* So just ignore the read bit for this command.
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*/
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if (i2c_start_transfer(bus, addr, 0)) {
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goto error;
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}
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ret = i2c_send(bus, s->smb_data1);
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if (ret) {
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goto error;
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}
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if (i2c_start_transfer(bus, addr, 1)) {
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goto error;
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}
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s->in_i2c_block_read = true;
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s->smb_blkdata = i2c_recv(s->smbus);
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s->op_done = false;
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s->smb_stat |= STS_HOST_BUSY | STS_BYTE_DONE;
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goto out;
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case PROT_BLOCK_DATA:
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if (read) {
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ret = smbus_read_block(bus, addr, cmd, s->smb_data,
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sizeof(s->smb_data), !s->i2c_enable,
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!s->i2c_enable);
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if (ret < 0) {
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goto error;
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}
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s->smb_index = 0;
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s->op_done = false;
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if (s->smb_auxctl & AUX_BLK) {
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s->smb_stat |= STS_INTR;
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} else {
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s->smb_blkdata = s->smb_data[0];
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s->smb_stat |= STS_HOST_BUSY | STS_BYTE_DONE;
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}
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s->smb_data0 = ret;
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goto out;
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} else {
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if (s->smb_auxctl & AUX_BLK) {
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if (s->smb_index != s->smb_data0) {
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s->smb_index = 0;
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goto error;
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}
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/* Data is already all written to the queue, just do
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the operation. */
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s->smb_index = 0;
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ret = smbus_write_block(bus, addr, cmd, s->smb_data,
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s->smb_data0, !s->i2c_enable);
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if (ret < 0) {
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goto error;
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}
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s->op_done = true;
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s->smb_stat |= STS_INTR;
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s->smb_stat &= ~STS_HOST_BUSY;
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} else {
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s->op_done = false;
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s->smb_stat |= STS_HOST_BUSY | STS_BYTE_DONE;
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s->smb_data[0] = s->smb_blkdata;
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s->smb_index = 0;
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ret = 0;
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}
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goto out;
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}
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break;
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default:
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goto error;
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}
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abort();
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data16:
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if (ret < 0) {
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goto error;
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}
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s->smb_data1 = ret >> 8;
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data8:
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if (ret < 0) {
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goto error;
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}
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s->smb_data0 = ret;
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done:
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if (ret < 0) {
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goto error;
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}
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s->smb_stat |= STS_INTR;
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out:
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return;
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error:
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s->smb_stat |= STS_DEV_ERR;
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return;
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}
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static void smb_transaction_start(PMSMBus *s)
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{
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if (s->smb_ctl & CTL_INTREN) {
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smb_transaction(s);
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s->start_transaction_on_status_read = false;
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} else {
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/* Do not execute immediately the command; it will be
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* executed when guest will read SMB_STAT register. This
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* is to work around a bug in AMIBIOS (that is working
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* around another bug in some specific hardware) where
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* it waits for STS_HOST_BUSY to be set before waiting
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* checking for status. If STS_HOST_BUSY doesn't get
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* set, it gets stuck. */
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s->smb_stat |= STS_HOST_BUSY;
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s->start_transaction_on_status_read = true;
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}
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}
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static bool
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smb_irq_value(PMSMBus *s)
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{
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return ((s->smb_stat & ~STS_HOST_BUSY) != 0) && (s->smb_ctl & CTL_INTREN);
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}
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static bool
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smb_byte_by_byte(PMSMBus *s)
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{
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if (s->op_done) {
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return false;
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}
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if (s->in_i2c_block_read) {
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return true;
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}
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return !(s->smb_auxctl & AUX_BLK);
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}
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static void smb_ioport_writeb(void *opaque, hwaddr addr, uint64_t val,
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unsigned width)
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{
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PMSMBus *s = opaque;
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uint8_t clear_byte_done;
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SMBUS_DPRINTF("SMB writeb port=0x%04" HWADDR_PRIx
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" val=0x%02" PRIx64 "\n", addr, val);
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switch(addr) {
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case SMBHSTSTS:
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clear_byte_done = s->smb_stat & val & STS_BYTE_DONE;
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s->smb_stat &= ~(val & ~STS_HOST_BUSY);
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if (clear_byte_done && smb_byte_by_byte(s)) {
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uint8_t read = s->smb_addr & 0x01;
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if (s->in_i2c_block_read) {
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/* See comment below PROT_I2C_BLOCK_READ above. */
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read = 1;
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}
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s->smb_index++;
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if (s->smb_index >= PM_SMBUS_MAX_MSG_SIZE) {
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s->smb_index = 0;
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}
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if (!read && s->smb_index == s->smb_data0) {
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uint8_t prot = (s->smb_ctl >> 2) & 0x07;
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uint8_t cmd = s->smb_cmd;
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uint8_t addr = s->smb_addr >> 1;
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int ret;
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if (prot == PROT_I2C_BLOCK_READ) {
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s->smb_stat |= STS_DEV_ERR;
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goto out;
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}
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ret = smbus_write_block(s->smbus, addr, cmd, s->smb_data,
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s->smb_data0, !s->i2c_enable);
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if (ret < 0) {
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s->smb_stat |= STS_DEV_ERR;
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goto out;
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}
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s->op_done = true;
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s->smb_stat |= STS_INTR;
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s->smb_stat &= ~STS_HOST_BUSY;
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} else if (!read) {
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s->smb_data[s->smb_index] = s->smb_blkdata;
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s->smb_stat |= STS_BYTE_DONE;
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} else if (s->smb_ctl & CTL_LAST_BYTE) {
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s->op_done = true;
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if (s->in_i2c_block_read) {
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s->in_i2c_block_read = false;
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s->smb_blkdata = i2c_recv(s->smbus);
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i2c_nack(s->smbus);
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i2c_end_transfer(s->smbus);
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} else {
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s->smb_blkdata = s->smb_data[s->smb_index];
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}
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s->smb_index = 0;
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s->smb_stat |= STS_INTR;
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s->smb_stat &= ~STS_HOST_BUSY;
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} else {
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if (s->in_i2c_block_read) {
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s->smb_blkdata = i2c_recv(s->smbus);
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} else {
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s->smb_blkdata = s->smb_data[s->smb_index];
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}
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s->smb_stat |= STS_BYTE_DONE;
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}
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}
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break;
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case SMBHSTCNT:
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s->smb_ctl = val & ~CTL_START; /* CTL_START always reads 0 */
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if (val & CTL_START) {
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if (!s->op_done) {
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s->smb_index = 0;
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s->op_done = true;
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if (s->in_i2c_block_read) {
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s->in_i2c_block_read = false;
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i2c_end_transfer(s->smbus);
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}
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}
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smb_transaction_start(s);
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}
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if (s->smb_ctl & CTL_KILL) {
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s->op_done = true;
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s->smb_index = 0;
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s->smb_stat |= STS_FAILED;
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s->smb_stat &= ~STS_HOST_BUSY;
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}
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break;
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case SMBHSTCMD:
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s->smb_cmd = val;
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break;
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case SMBHSTADD:
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s->smb_addr = val;
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break;
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case SMBHSTDAT0:
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s->smb_data0 = val;
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break;
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case SMBHSTDAT1:
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s->smb_data1 = val;
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break;
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case SMBBLKDAT:
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if (s->smb_index >= PM_SMBUS_MAX_MSG_SIZE) {
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s->smb_index = 0;
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}
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if (s->smb_auxctl & AUX_BLK) {
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s->smb_data[s->smb_index++] = val;
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} else {
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s->smb_blkdata = val;
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}
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break;
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case SMBAUXCTL:
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s->smb_auxctl = val & AUX_MASK;
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break;
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default:
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break;
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}
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out:
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if (s->set_irq) {
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s->set_irq(s, smb_irq_value(s));
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}
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}
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static uint64_t smb_ioport_readb(void *opaque, hwaddr addr, unsigned width)
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{
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PMSMBus *s = opaque;
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uint32_t val;
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switch(addr) {
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case SMBHSTSTS:
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val = s->smb_stat;
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if (s->start_transaction_on_status_read) {
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/* execute command now */
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s->start_transaction_on_status_read = false;
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s->smb_stat &= ~STS_HOST_BUSY;
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smb_transaction(s);
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}
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break;
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case SMBHSTCNT:
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val = s->smb_ctl & CTL_RETURN_MASK;
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break;
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case SMBHSTCMD:
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val = s->smb_cmd;
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break;
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case SMBHSTADD:
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val = s->smb_addr;
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break;
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case SMBHSTDAT0:
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val = s->smb_data0;
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break;
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case SMBHSTDAT1:
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val = s->smb_data1;
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break;
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case SMBBLKDAT:
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if (s->smb_auxctl & AUX_BLK && !s->in_i2c_block_read) {
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if (s->smb_index >= PM_SMBUS_MAX_MSG_SIZE) {
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s->smb_index = 0;
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}
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val = s->smb_data[s->smb_index++];
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if (!s->op_done && s->smb_index == s->smb_data0) {
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s->op_done = true;
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s->smb_index = 0;
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s->smb_stat &= ~STS_HOST_BUSY;
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}
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} else {
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val = s->smb_blkdata;
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}
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break;
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case SMBAUXCTL:
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val = s->smb_auxctl;
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break;
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default:
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val = 0;
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break;
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}
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SMBUS_DPRINTF("SMB readb port=0x%04" HWADDR_PRIx " val=0x%02x\n",
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addr, val);
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if (s->set_irq) {
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s->set_irq(s, smb_irq_value(s));
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}
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return val;
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}
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static void pm_smbus_reset(PMSMBus *s)
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{
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s->op_done = true;
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s->smb_index = 0;
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s->smb_stat = 0;
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}
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static const MemoryRegionOps pm_smbus_ops = {
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.read = smb_ioport_readb,
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.write = smb_ioport_writeb,
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.valid.min_access_size = 1,
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.valid.max_access_size = 1,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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bool pm_smbus_vmstate_needed(void)
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{
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MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
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return !mc->smbus_no_migration_support;
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}
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const VMStateDescription pmsmb_vmstate = {
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.name = "pmsmb",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8(smb_stat, PMSMBus),
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VMSTATE_UINT8(smb_ctl, PMSMBus),
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VMSTATE_UINT8(smb_cmd, PMSMBus),
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VMSTATE_UINT8(smb_addr, PMSMBus),
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VMSTATE_UINT8(smb_data0, PMSMBus),
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VMSTATE_UINT8(smb_data1, PMSMBus),
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VMSTATE_UINT32(smb_index, PMSMBus),
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VMSTATE_UINT8_ARRAY(smb_data, PMSMBus, PM_SMBUS_MAX_MSG_SIZE),
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VMSTATE_UINT8(smb_auxctl, PMSMBus),
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VMSTATE_UINT8(smb_blkdata, PMSMBus),
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VMSTATE_BOOL(i2c_enable, PMSMBus),
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VMSTATE_BOOL(op_done, PMSMBus),
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VMSTATE_BOOL(in_i2c_block_read, PMSMBus),
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VMSTATE_BOOL(start_transaction_on_status_read, PMSMBus),
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VMSTATE_END_OF_LIST()
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}
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};
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void pm_smbus_init(DeviceState *parent, PMSMBus *smb, bool force_aux_blk)
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{
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smb->op_done = true;
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smb->reset = pm_smbus_reset;
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smb->smbus = i2c_init_bus(parent, "i2c");
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if (force_aux_blk) {
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smb->smb_auxctl |= AUX_BLK;
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}
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memory_region_init_io(&smb->io, OBJECT(parent), &pm_smbus_ops, smb,
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"pm-smbus", 64);
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}
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