6a9801106e
With previous cleanups made, the 32-bit and 64-bit pte_check*() functions are pretty trivial and only have one call site. This patch therefore clarifies the overall code flow by folding those functions into their call site. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
596 lines
18 KiB
C
596 lines
18 KiB
C
/*
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* PowerPC MMU, TLB and BAT emulation helpers for QEMU.
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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* Copyright (c) 2013 David Gibson, IBM Corporation
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h"
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#include "helper.h"
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#include "sysemu/kvm.h"
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#include "kvm_ppc.h"
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#include "mmu-hash32.h"
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//#define DEBUG_MMU
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//#define DEBUG_BAT
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#ifdef DEBUG_MMU
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# define LOG_MMU(...) qemu_log(__VA_ARGS__)
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# define LOG_MMU_STATE(env) log_cpu_state((env), 0)
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#else
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# define LOG_MMU(...) do { } while (0)
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# define LOG_MMU_STATE(...) do { } while (0)
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#endif
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#ifdef DEBUG_BATS
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# define LOG_BATS(...) qemu_log(__VA_ARGS__)
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#else
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# define LOG_BATS(...) do { } while (0)
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#endif
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struct mmu_ctx_hash32 {
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hwaddr raddr; /* Real address */
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int prot; /* Protection bits */
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int key; /* Access key */
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int nx; /* Non-execute area */
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};
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static int ppc_hash32_pp_check(int key, int pp, int nx)
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{
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int access;
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/* Compute access rights */
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access = 0;
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if (key == 0) {
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switch (pp) {
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case 0x0:
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case 0x1:
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case 0x2:
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access |= PAGE_WRITE;
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/* No break here */
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case 0x3:
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access |= PAGE_READ;
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break;
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}
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} else {
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switch (pp) {
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case 0x0:
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access = 0;
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break;
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case 0x1:
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case 0x3:
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access = PAGE_READ;
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break;
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case 0x2:
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access = PAGE_READ | PAGE_WRITE;
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break;
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}
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}
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if (nx == 0) {
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access |= PAGE_EXEC;
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}
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return access;
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}
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static int ppc_hash32_check_prot(int prot, int rwx)
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{
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int ret;
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if (rwx == 2) {
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if (prot & PAGE_EXEC) {
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ret = 0;
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} else {
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ret = -2;
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}
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} else if (rwx) {
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if (prot & PAGE_WRITE) {
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ret = 0;
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} else {
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ret = -2;
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}
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} else {
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if (prot & PAGE_READ) {
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ret = 0;
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} else {
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ret = -2;
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}
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}
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return ret;
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}
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/* Perform BAT hit & translation */
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static void hash32_bat_size_prot(CPUPPCState *env, target_ulong *blp,
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int *validp, int *protp, target_ulong *BATu,
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target_ulong *BATl)
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{
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target_ulong bl;
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int pp, valid, prot;
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bl = (*BATu & BATU32_BL) << 15;
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valid = 0;
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prot = 0;
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if (((msr_pr == 0) && (*BATu & BATU32_VS)) ||
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((msr_pr != 0) && (*BATu & BATU32_VP))) {
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valid = 1;
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pp = *BATl & BATL32_PP;
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if (pp != 0) {
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prot = PAGE_READ | PAGE_EXEC;
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if (pp == 0x2) {
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prot |= PAGE_WRITE;
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}
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}
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}
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*blp = bl;
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*validp = valid;
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*protp = prot;
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}
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static void hash32_bat_601_size_prot(CPUPPCState *env, target_ulong *blp,
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int *validp, int *protp,
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target_ulong *BATu, target_ulong *BATl)
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{
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target_ulong bl;
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int key, pp, valid, prot;
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bl = (*BATl & BATL32_601_BL) << 17;
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LOG_BATS("b %02x ==> bl " TARGET_FMT_lx " msk " TARGET_FMT_lx "\n",
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(uint8_t)(*BATl & BATL32_601_BL), bl, ~bl);
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prot = 0;
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valid = !!(*BATl & BATL32_601_V);
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if (valid) {
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pp = *BATu & BATU32_601_PP;
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if (msr_pr == 0) {
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key = !!(*BATu & BATU32_601_KS);
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} else {
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key = !!(*BATu & BATU32_601_KP);
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}
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prot = ppc_hash32_pp_check(key, pp, 0);
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}
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*blp = bl;
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*validp = valid;
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*protp = prot;
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}
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static int ppc_hash32_get_bat(CPUPPCState *env, struct mmu_ctx_hash32 *ctx,
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target_ulong virtual, int rwx)
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{
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target_ulong *BATlt, *BATut, *BATu, *BATl;
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target_ulong BEPIl, BEPIu, bl;
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int i, valid, prot;
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int ret = -1;
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LOG_BATS("%s: %cBAT v " TARGET_FMT_lx "\n", __func__,
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rwx == 2 ? 'I' : 'D', virtual);
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if (rwx == 2) {
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BATlt = env->IBAT[1];
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BATut = env->IBAT[0];
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} else {
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BATlt = env->DBAT[1];
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BATut = env->DBAT[0];
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}
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for (i = 0; i < env->nb_BATs; i++) {
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BATu = &BATut[i];
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BATl = &BATlt[i];
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BEPIu = *BATu & BATU32_BEPIU;
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BEPIl = *BATu & BATU32_BEPIL;
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if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
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hash32_bat_601_size_prot(env, &bl, &valid, &prot, BATu, BATl);
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} else {
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hash32_bat_size_prot(env, &bl, &valid, &prot, BATu, BATl);
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}
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LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
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" BATl " TARGET_FMT_lx "\n", __func__,
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type == ACCESS_CODE ? 'I' : 'D', i, virtual, *BATu, *BATl);
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if ((virtual & BATU32_BEPIU) == BEPIu &&
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((virtual & BATU32_BEPIL) & ~bl) == BEPIl) {
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/* BAT matches */
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if (valid != 0) {
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/* Get physical address */
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ctx->raddr = (*BATl & BATL32_BRPNU) |
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((virtual & BATU32_BEPIL & bl) | (*BATl & BATL32_BRPNL)) |
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(virtual & 0x0001F000);
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/* Compute access rights */
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ctx->prot = prot;
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ret = ppc_hash32_check_prot(ctx->prot, rwx);
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if (ret == 0) {
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LOG_BATS("BAT %d match: r " TARGET_FMT_plx " prot=%c%c\n",
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i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',
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ctx->prot & PAGE_WRITE ? 'W' : '-');
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}
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break;
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}
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}
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}
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if (ret < 0) {
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#if defined(DEBUG_BATS)
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if (qemu_log_enabled()) {
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LOG_BATS("no BAT match for " TARGET_FMT_lx ":\n", virtual);
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for (i = 0; i < 4; i++) {
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BATu = &BATut[i];
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BATl = &BATlt[i];
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BEPIu = *BATu & BATU32_BEPIU;
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BEPIl = *BATu & BATU32_BEPIL;
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bl = (*BATu & 0x00001FFC) << 15;
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LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
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" BATl " TARGET_FMT_lx "\n\t" TARGET_FMT_lx " "
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TARGET_FMT_lx " " TARGET_FMT_lx "\n",
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__func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
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*BATu, *BATl, BEPIu, BEPIl, bl);
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}
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}
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#endif
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}
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/* No hit */
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return ret;
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}
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static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr,
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target_ulong eaddr, int rwx,
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hwaddr *raddr, int *prot)
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{
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int key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS));
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LOG_MMU("direct store...\n");
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if ((sr & 0x1FF00000) >> 20 == 0x07f) {
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/* Memory-forced I/O controller interface access */
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/* If T=1 and BUID=x'07F', the 601 performs a memory access
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* to SR[28-31] LA[4-31], bypassing all protection mechanisms.
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*/
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*raddr = ((sr & 0xF) << 28) | (eaddr & 0x0FFFFFFF);
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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return 0;
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}
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if (rwx == 2) {
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/* No code fetch is allowed in direct-store areas */
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return -4;
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}
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switch (env->access_type) {
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case ACCESS_INT:
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/* Integer load/store : only access allowed */
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break;
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case ACCESS_FLOAT:
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/* Floating point load/store */
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return -4;
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case ACCESS_RES:
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/* lwarx, ldarx or srwcx. */
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return -4;
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case ACCESS_CACHE:
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/* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
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/* Should make the instruction do no-op.
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* As it already do no-op, it's quite easy :-)
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*/
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*raddr = eaddr;
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return 0;
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case ACCESS_EXT:
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/* eciwx or ecowx */
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return -4;
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default:
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qemu_log("ERROR: instruction should not need "
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"address translation\n");
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return -4;
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}
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if ((rwx == 1 || key != 1) && (rwx == 0 || key != 0)) {
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*raddr = eaddr;
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return 2;
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} else {
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return -2;
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}
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}
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static int ppc_hash32_pte_update_flags(struct mmu_ctx_hash32 *ctx, uint32_t *pte1p,
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int ret, int rwx)
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{
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int store = 0;
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/* Update page flags */
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if (!(*pte1p & HPTE32_R_R)) {
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/* Update accessed flag */
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*pte1p |= HPTE32_R_R;
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store = 1;
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}
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if (!(*pte1p & HPTE32_R_C)) {
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if (rwx == 1 && ret == 0) {
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/* Update changed flag */
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*pte1p |= HPTE32_R_C;
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store = 1;
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} else {
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/* Force page fault for first write access */
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ctx->prot &= ~PAGE_WRITE;
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}
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}
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return store;
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}
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hwaddr get_pteg_offset32(CPUPPCState *env, hwaddr hash)
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{
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return (hash * HASH_PTEG_SIZE_32) & env->htab_mask;
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}
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static hwaddr ppc_hash32_pteg_search(CPUPPCState *env, hwaddr pteg_off,
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bool secondary, target_ulong ptem,
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ppc_hash_pte32_t *pte)
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{
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hwaddr pte_offset = pteg_off;
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target_ulong pte0, pte1;
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int i;
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for (i = 0; i < HPTES_PER_GROUP; i++) {
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pte0 = ppc_hash32_load_hpte0(env, pte_offset);
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pte1 = ppc_hash32_load_hpte1(env, pte_offset);
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if ((pte0 & HPTE32_V_VALID)
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&& (secondary == !!(pte0 & HPTE32_V_SECONDARY))
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&& HPTE32_V_COMPARE(pte0, ptem)) {
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pte->pte0 = pte0;
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pte->pte1 = pte1;
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return pte_offset;
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}
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pte_offset += HASH_PTE_SIZE_32;
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}
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return -1;
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}
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static hwaddr ppc_hash32_htab_lookup(CPUPPCState *env,
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target_ulong sr, target_ulong eaddr,
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ppc_hash_pte32_t *pte)
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{
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hwaddr pteg_off, pte_offset;
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hwaddr hash;
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uint32_t vsid, pgidx, ptem;
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vsid = sr & SR32_VSID;
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pgidx = (eaddr & ~SEGMENT_MASK_256M) >> TARGET_PAGE_BITS;
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hash = vsid ^ pgidx;
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ptem = (vsid << 7) | (pgidx >> 10);
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/* Page address translation */
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LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
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" hash " TARGET_FMT_plx "\n",
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env->htab_base, env->htab_mask, hash);
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/* Primary PTEG lookup */
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LOG_MMU("0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
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" vsid=%" PRIx32 " ptem=%" PRIx32
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" hash=" TARGET_FMT_plx "\n",
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env->htab_base, env->htab_mask, vsid, ptem, hash);
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pteg_off = get_pteg_offset32(env, hash);
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pte_offset = ppc_hash32_pteg_search(env, pteg_off, 0, ptem, pte);
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if (pte_offset == -1) {
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/* Secondary PTEG lookup */
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LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
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" vsid=%" PRIx32 " api=%" PRIx32
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" hash=" TARGET_FMT_plx "\n", env->htab_base,
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env->htab_mask, vsid, ptem, ~hash);
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pteg_off = get_pteg_offset32(env, ~hash);
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pte_offset = ppc_hash32_pteg_search(env, pteg_off, 1, ptem, pte);
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}
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return pte_offset;
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}
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static int ppc_hash32_translate(CPUPPCState *env, struct mmu_ctx_hash32 *ctx,
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target_ulong eaddr, int rwx)
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{
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int ret;
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target_ulong sr;
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hwaddr pte_offset;
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ppc_hash_pte32_t pte;
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assert((rwx == 0) || (rwx == 1) || (rwx == 2));
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/* 1. Handle real mode accesses */
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if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
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/* Translation is off */
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ctx->raddr = eaddr;
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ctx->prot = PAGE_READ | PAGE_EXEC | PAGE_WRITE;
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return 0;
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}
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/* 2. Check Block Address Translation entries (BATs) */
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if (env->nb_BATs != 0) {
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ret = ppc_hash32_get_bat(env, ctx, eaddr, rwx);
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if (ret == 0) {
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return 0;
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}
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}
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/* 3. Look up the Segment Register */
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sr = env->sr[eaddr >> 28];
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/* 4. Handle direct store segments */
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if (sr & SR32_T) {
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return ppc_hash32_direct_store(env, sr, eaddr, rwx,
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&ctx->raddr, &ctx->prot);
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}
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/* 5. Check for segment level no-execute violation */
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ctx->nx = !!(sr & SR32_NX);
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if ((rwx == 2) && ctx->nx) {
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return -3;
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}
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/* 6. Locate the PTE in the hash table */
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pte_offset = ppc_hash32_htab_lookup(env, sr, eaddr, &pte);
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if (pte_offset == -1) {
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return -1;
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}
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LOG_MMU("found PTE at offset %08" HWADDR_PRIx "\n", pte_offset);
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/* 7. Check access permissions */
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ctx->key = (((sr & SR32_KP) && (msr_pr != 0)) ||
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((sr & SR32_KS) && (msr_pr == 0))) ? 1 : 0;
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int access, pp;
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pp = pte.pte1 & HPTE32_R_PP;
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/* Compute access rights */
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access = ppc_hash32_pp_check(ctx->key, pp, ctx->nx);
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/* Keep the matching PTE informations */
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ctx->raddr = pte.pte1;
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ctx->prot = access;
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ret = ppc_hash32_check_prot(ctx->prot, rwx);
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if (ret == 0) {
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/* Access granted */
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LOG_MMU("PTE access granted !\n");
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} else {
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/* Access right violation */
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LOG_MMU("PTE access rejected\n");
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}
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/* Update page flags */
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if (ppc_hash32_pte_update_flags(ctx, &pte.pte1, ret, rwx) == 1) {
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ppc_hash32_store_hpte1(env, pte_offset, pte.pte1);
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}
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return ret;
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}
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hwaddr ppc_hash32_get_phys_page_debug(CPUPPCState *env, target_ulong addr)
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{
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struct mmu_ctx_hash32 ctx;
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/* FIXME: Will not behave sanely for direct store segments, but
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* they're almost never used */
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if (unlikely(ppc_hash32_translate(env, &ctx, addr, 0)
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!= 0)) {
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return -1;
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}
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return ctx.raddr & TARGET_PAGE_MASK;
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}
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int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rwx,
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int mmu_idx)
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{
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struct mmu_ctx_hash32 ctx;
|
|
int ret = 0;
|
|
|
|
ret = ppc_hash32_translate(env, &ctx, address, rwx);
|
|
if (ret == 0) {
|
|
tlb_set_page(env, address & TARGET_PAGE_MASK,
|
|
ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
|
|
mmu_idx, TARGET_PAGE_SIZE);
|
|
ret = 0;
|
|
} else if (ret < 0) {
|
|
LOG_MMU_STATE(env);
|
|
if (rwx == 2) {
|
|
switch (ret) {
|
|
case -1:
|
|
/* No matches in page tables or TLB */
|
|
env->exception_index = POWERPC_EXCP_ISI;
|
|
env->error_code = 0x40000000;
|
|
break;
|
|
case -2:
|
|
/* Access rights violation */
|
|
env->exception_index = POWERPC_EXCP_ISI;
|
|
env->error_code = 0x08000000;
|
|
break;
|
|
case -3:
|
|
/* No execute protection violation */
|
|
env->exception_index = POWERPC_EXCP_ISI;
|
|
env->error_code = 0x10000000;
|
|
break;
|
|
case -4:
|
|
/* Direct store exception */
|
|
/* No code fetch is allowed in direct-store areas */
|
|
env->exception_index = POWERPC_EXCP_ISI;
|
|
env->error_code = 0x10000000;
|
|
break;
|
|
}
|
|
} else {
|
|
switch (ret) {
|
|
case -1:
|
|
/* No matches in page tables or TLB */
|
|
env->exception_index = POWERPC_EXCP_DSI;
|
|
env->error_code = 0;
|
|
env->spr[SPR_DAR] = address;
|
|
if (rwx == 1) {
|
|
env->spr[SPR_DSISR] = 0x42000000;
|
|
} else {
|
|
env->spr[SPR_DSISR] = 0x40000000;
|
|
}
|
|
break;
|
|
case -2:
|
|
/* Access rights violation */
|
|
env->exception_index = POWERPC_EXCP_DSI;
|
|
env->error_code = 0;
|
|
env->spr[SPR_DAR] = address;
|
|
if (rwx == 1) {
|
|
env->spr[SPR_DSISR] = 0x0A000000;
|
|
} else {
|
|
env->spr[SPR_DSISR] = 0x08000000;
|
|
}
|
|
break;
|
|
case -4:
|
|
/* Direct store exception */
|
|
switch (env->access_type) {
|
|
case ACCESS_FLOAT:
|
|
/* Floating point load/store */
|
|
env->exception_index = POWERPC_EXCP_ALIGN;
|
|
env->error_code = POWERPC_EXCP_ALIGN_FP;
|
|
env->spr[SPR_DAR] = address;
|
|
break;
|
|
case ACCESS_RES:
|
|
/* lwarx, ldarx or stwcx. */
|
|
env->exception_index = POWERPC_EXCP_DSI;
|
|
env->error_code = 0;
|
|
env->spr[SPR_DAR] = address;
|
|
if (rwx == 1) {
|
|
env->spr[SPR_DSISR] = 0x06000000;
|
|
} else {
|
|
env->spr[SPR_DSISR] = 0x04000000;
|
|
}
|
|
break;
|
|
case ACCESS_EXT:
|
|
/* eciwx or ecowx */
|
|
env->exception_index = POWERPC_EXCP_DSI;
|
|
env->error_code = 0;
|
|
env->spr[SPR_DAR] = address;
|
|
if (rwx == 1) {
|
|
env->spr[SPR_DSISR] = 0x06100000;
|
|
} else {
|
|
env->spr[SPR_DSISR] = 0x04100000;
|
|
}
|
|
break;
|
|
default:
|
|
printf("DSI: invalid exception (%d)\n", ret);
|
|
env->exception_index = POWERPC_EXCP_PROGRAM;
|
|
env->error_code =
|
|
POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
|
|
env->spr[SPR_DAR] = address;
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
#if 0
|
|
printf("%s: set exception to %d %02x\n", __func__,
|
|
env->exception, env->error_code);
|
|
#endif
|
|
ret = 1;
|
|
}
|
|
|
|
return ret;
|
|
}
|