* make PowerPC NVRAM accessors generic to be able to use a MacIO NVRAM instead of the M48T59 one * split PowerMac targets code: - move all PowerMac related definitions and prototypes into hw/ppc_mac.h - add hw/mac_dbdma.c, hw/mac_nvram.c and macio.c which implements shared PowerMac devices - define the g3bw machine in a new hw/ppc_oldworld.c file * Fix the g3bw target: - fix the Grackle host PCI device - connect the Heathrow PIC to the PowerPC 6xx bus pins git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3475 c046a42c-6fe2-441c-8c8c-71466251a162
178 lines
4.5 KiB
C
178 lines
4.5 KiB
C
/*
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* Heathrow PIC support (OldWorld PowerMac)
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*
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* Copyright (c) 2005-2007 Fabrice Bellard
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h"
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#include "ppc_mac.h"
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//#define DEBUG
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typedef struct HeathrowPIC {
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uint32_t events;
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uint32_t mask;
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uint32_t levels;
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uint32_t level_triggered;
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} HeathrowPIC;
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typedef struct HeathrowPICS {
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HeathrowPIC pics[2];
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qemu_irq *irqs;
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} HeathrowPICS;
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static inline int check_irq(HeathrowPIC *pic)
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{
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return (pic->events | (pic->levels & pic->level_triggered)) & pic->mask;
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}
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/* update the CPU irq state */
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static void heathrow_pic_update(HeathrowPICS *s)
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{
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if (check_irq(&s->pics[0]) || check_irq(&s->pics[1])) {
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qemu_irq_raise(s->irqs[0]);
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} else {
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qemu_irq_lower(s->irqs[0]);
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}
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}
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static void pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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HeathrowPICS *s = opaque;
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HeathrowPIC *pic;
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unsigned int n;
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#ifdef TARGET_WORDS_BIGENDIAN
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value = bswap32(value);
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#endif
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n = ((addr & 0xfff) - 0x10) >> 4;
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#ifdef DEBUG
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printf("pic_writel: " PADDRX " %u: %08x\n", addr, n, value);
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#endif
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if (n >= 2)
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return;
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pic = &s->pics[n];
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switch(addr & 0xf) {
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case 0x04:
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pic->mask = value;
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heathrow_pic_update(s);
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break;
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case 0x08:
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/* do not reset level triggered IRQs */
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value &= ~pic->level_triggered;
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pic->events &= ~value;
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heathrow_pic_update(s);
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break;
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default:
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break;
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}
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}
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static uint32_t pic_readl (void *opaque, target_phys_addr_t addr)
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{
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HeathrowPICS *s = opaque;
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HeathrowPIC *pic;
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unsigned int n;
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uint32_t value;
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n = ((addr & 0xfff) - 0x10) >> 4;
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if (n >= 2) {
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value = 0;
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} else {
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pic = &s->pics[n];
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switch(addr & 0xf) {
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case 0x0:
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value = pic->events;
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break;
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case 0x4:
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value = pic->mask;
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break;
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case 0xc:
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value = pic->levels;
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break;
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default:
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value = 0;
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break;
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}
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}
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#ifdef DEBUG
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printf("pic_readl: " PADDRX " %u: %08x\n", addr, n, value);
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#endif
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#ifdef TARGET_WORDS_BIGENDIAN
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value = bswap32(value);
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#endif
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return value;
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}
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static CPUWriteMemoryFunc *pic_write[] = {
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&pic_writel,
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&pic_writel,
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&pic_writel,
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};
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static CPUReadMemoryFunc *pic_read[] = {
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&pic_readl,
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&pic_readl,
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&pic_readl,
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};
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static void heathrow_pic_set_irq(void *opaque, int num, int level)
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{
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HeathrowPICS *s = opaque;
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HeathrowPIC *pic;
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unsigned int irq_bit;
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#if defined(DEBUG)
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{
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static int last_level[64];
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if (last_level[num] != level) {
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printf("set_irq: num=0x%02x level=%d\n", num, level);
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last_level[num] = level;
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}
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}
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#endif
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pic = &s->pics[1 - (num >> 5)];
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irq_bit = 1 << (num & 0x1f);
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if (level) {
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pic->events |= irq_bit & ~pic->level_triggered;
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pic->levels |= irq_bit;
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} else {
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pic->levels &= ~irq_bit;
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}
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heathrow_pic_update(s);
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}
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qemu_irq *heathrow_pic_init(int *pmem_index,
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int nb_cpus, qemu_irq **irqs)
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{
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HeathrowPICS *s;
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s = qemu_mallocz(sizeof(HeathrowPICS));
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s->pics[0].level_triggered = 0;
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s->pics[1].level_triggered = 0x1ff00000;
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/* only 1 CPU */
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s->irqs = irqs[0];
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*pmem_index = cpu_register_io_memory(0, pic_read, pic_write, s);
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return qemu_allocate_irqs(heathrow_pic_set_irq, s, 64);
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}
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