ee951a37d8
Nothing prevented IRQ sharing on the ISA bus in principle. Not all boards supported this, neither each and every card nor driver and OS. Still, there existed valid IRQ sharing scenarios, (at least) two of them can also be found in QEMU: >2 PC UARTs and the PREP IDE buses. So remove this artificial restriction from our ISA model. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
54 lines
1.5 KiB
C
54 lines
1.5 KiB
C
#ifndef HW_ISA_H
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#define HW_ISA_H
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/* ISA bus */
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#include "ioport.h"
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#include "qdev.h"
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typedef struct ISABus ISABus;
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typedef struct ISADevice ISADevice;
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typedef struct ISADeviceInfo ISADeviceInfo;
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struct ISADevice {
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DeviceState qdev;
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uint32_t isairq[2];
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int nirqs;
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uint16_t ioports[32];
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int nioports;
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};
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typedef int (*isa_qdev_initfn)(ISADevice *dev);
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struct ISADeviceInfo {
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DeviceInfo qdev;
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isa_qdev_initfn init;
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};
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ISABus *isa_bus_new(DeviceState *dev);
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void isa_bus_irqs(qemu_irq *irqs);
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qemu_irq isa_get_irq(int isairq);
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void isa_init_irq(ISADevice *dev, qemu_irq *p, int isairq);
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void isa_init_ioport(ISADevice *dev, uint16_t ioport);
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void isa_init_ioport_range(ISADevice *dev, uint16_t start, uint16_t length);
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void isa_qdev_register(ISADeviceInfo *info);
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ISADevice *isa_create(const char *name);
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ISADevice *isa_try_create(const char *name);
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ISADevice *isa_create_simple(const char *name);
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extern target_phys_addr_t isa_mem_base;
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void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
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/* dma.c */
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int DMA_get_channel_mode (int nchan);
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int DMA_read_memory (int nchan, void *buf, int pos, int size);
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int DMA_write_memory (int nchan, void *buf, int pos, int size);
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void DMA_hold_DREQ (int nchan);
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void DMA_release_DREQ (int nchan);
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void DMA_schedule(int nchan);
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void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit);
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void DMA_register_channel (int nchan,
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DMA_transfer_handler transfer_handler,
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void *opaque);
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#endif
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