6ebbf39000
allowing support of more than 2 mmu access modes. Add backward compatibility is_user variable in targets code when needed. Implement per target cpu_mmu_index function, avoiding duplicated code and #ifdef TARGET_xxx in softmmu core functions. Implement per target mmu modes definitions. As an example, add PowerPC hypervisor mode definition and Alpha executive and kernel modes definitions. Optimize PowerPC case, precomputing mmu_idx when MSR register changes and using the same definition in code translation code. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3384 c046a42c-6fe2-441c-8c8c-71466251a162
160 lines
4.1 KiB
C
160 lines
4.1 KiB
C
/*
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* M68K helper routines
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*
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* Copyright (c) 2007 CodeSourcery
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "exec.h"
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#if defined(CONFIG_USER_ONLY)
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void do_interrupt(int is_hw)
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{
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env->exception_index = -1;
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}
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#else
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extern int semihosting_enabled;
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#define MMUSUFFIX _mmu
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#define GETPC() (__builtin_return_address(0))
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#define SHIFT 0
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#include "softmmu_template.h"
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#define SHIFT 1
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#include "softmmu_template.h"
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#define SHIFT 2
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#include "softmmu_template.h"
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#define SHIFT 3
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#include "softmmu_template.h"
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/* Try to fill the TLB and return an exception if error. If retaddr is
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NULL, it means that the function was called in C code (i.e. not
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from generated code or from helper.c) */
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/* XXX: fix it to restore all registers */
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void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
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{
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TranslationBlock *tb;
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CPUState *saved_env;
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target_phys_addr_t pc;
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int ret;
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/* XXX: hack to restore env in all cases, even if not called from
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generated code */
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saved_env = env;
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env = cpu_single_env;
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ret = cpu_m68k_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
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if (__builtin_expect(ret, 0)) {
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if (retaddr) {
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/* now we have a real cpu fault */
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pc = (target_phys_addr_t)retaddr;
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tb = tb_find_pc(pc);
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if (tb) {
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/* the PC is inside the translated code. It means that we have
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a virtual CPU fault */
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cpu_restore_state(tb, env, pc, NULL);
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}
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}
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cpu_loop_exit();
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}
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env = saved_env;
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}
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static void do_rte(void)
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{
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uint32_t sp;
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uint32_t fmt;
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sp = env->aregs[7];
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fmt = ldl_kernel(sp);
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env->pc = ldl_kernel(sp + 4);
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sp |= (fmt >> 28) & 3;
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env->sr = fmt & 0xffff;
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m68k_switch_sp(env);
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env->aregs[7] = sp + 8;
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}
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void do_interrupt(int is_hw)
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{
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uint32_t sp;
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uint32_t fmt;
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uint32_t retaddr;
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uint32_t vector;
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fmt = 0;
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retaddr = env->pc;
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if (!is_hw) {
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switch (env->exception_index) {
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case EXCP_RTE:
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/* Return from an exception. */
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do_rte();
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return;
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case EXCP_HALT_INSN:
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if (semihosting_enabled
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&& (env->sr & SR_S) != 0
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&& (env->pc & 3) == 0
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&& lduw_code(env->pc - 4) == 0x4e71
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&& ldl_code(env->pc) == 0x4e7bf000) {
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env->pc += 4;
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do_m68k_semihosting(env, env->dregs[0]);
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return;
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}
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env->halted = 1;
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env->exception_index = EXCP_HLT;
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cpu_loop_exit();
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return;
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}
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if (env->exception_index >= EXCP_TRAP0
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&& env->exception_index <= EXCP_TRAP15) {
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/* Move the PC after the trap instruction. */
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retaddr += 2;
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}
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}
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vector = env->exception_index << 2;
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sp = env->aregs[7];
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fmt |= 0x40000000;
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fmt |= (sp & 3) << 28;
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fmt |= vector << 16;
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fmt |= env->sr;
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env->sr |= SR_S;
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if (is_hw) {
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env->sr = (env->sr & ~SR_I) | (env->pending_level << SR_I_SHIFT);
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env->sr &= ~SR_M;
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}
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m68k_switch_sp(env);
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/* ??? This could cause MMU faults. */
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sp &= ~3;
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sp -= 4;
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stl_kernel(sp, retaddr);
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sp -= 4;
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stl_kernel(sp, fmt);
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env->aregs[7] = sp;
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/* Jump to vector. */
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env->pc = ldl_kernel(env->vbr + vector);
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}
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#endif
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