Instead of casting an address within a uint8_t array to a uint32_t*, use stl_le_p(). This handles possibly misaligned addresses which would otherwise crash on some hosts. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Tested-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Signed-off-by: Jason Wang <jasowang@redhat.com>
688 lines
20 KiB
C
688 lines
20 KiB
C
/*
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* CTU CAN FD PCI device emulation
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* http://canbus.pages.fel.cvut.cz/
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*
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* Copyright (c) 2019 Jan Charvat (jancharvat.charvat@gmail.com)
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*
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* Based on Kvaser PCI CAN device (SJA1000 based) emulation implemented by
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* Jin Yang and Pavel Pisa
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "chardev/char.h"
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#include "hw/irq.h"
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#include "migration/vmstate.h"
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#include "net/can_emu.h"
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#include "ctucan_core.h"
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#ifndef DEBUG_CAN
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#define DEBUG_CAN 0
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#endif /*DEBUG_CAN*/
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#define DPRINTF(fmt, ...) \
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do { \
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if (DEBUG_CAN) { \
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qemu_log("[ctucan]: " fmt , ## __VA_ARGS__); \
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} \
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} while (0)
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static void ctucan_buff2frame(const uint8_t *buff, qemu_can_frame *frame)
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{
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frame->can_id = 0;
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frame->can_dlc = 0;
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frame->flags = 0;
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if (buff == NULL) {
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return;
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}
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{
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union ctu_can_fd_frame_form_w frame_form_w;
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union ctu_can_fd_identifier_w identifier_w;
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unsigned int ide;
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uint32_t w;
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w = le32_to_cpu(*(uint32_t *)buff);
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frame_form_w = (union ctu_can_fd_frame_form_w)w;
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frame->can_dlc = can_dlc2len(frame_form_w.s.dlc);
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w = le32_to_cpu(*(uint32_t *)(buff + 4));
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identifier_w = (union ctu_can_fd_identifier_w)w;
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ide = frame_form_w.s.ide;
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if (ide) {
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frame->can_id = (identifier_w.s.identifier_base << 18) |
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identifier_w.s.identifier_ext;
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frame->can_id |= QEMU_CAN_EFF_FLAG;
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} else {
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frame->can_id = identifier_w.s.identifier_base;
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}
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if (frame_form_w.s.esi_rsv) {
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frame->flags |= QEMU_CAN_FRMF_ESI;
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}
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if (frame_form_w.s.rtr) {
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frame->can_id |= QEMU_CAN_RTR_FLAG;
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}
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if (frame_form_w.s.fdf) { /*CAN FD*/
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frame->flags |= QEMU_CAN_FRMF_TYPE_FD;
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if (frame_form_w.s.brs) {
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frame->flags |= QEMU_CAN_FRMF_BRS;
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}
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}
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}
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memcpy(frame->data, buff + 0x10, 0x40);
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}
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static int ctucan_frame2buff(const qemu_can_frame *frame, uint8_t *buff)
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{
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unsigned int bytes_cnt = -1;
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memset(buff, 0, CTUCAN_MSG_MAX_LEN * sizeof(*buff));
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if (frame == NULL) {
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return bytes_cnt;
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}
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{
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union ctu_can_fd_frame_form_w frame_form_w;
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union ctu_can_fd_identifier_w identifier_w;
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frame_form_w.u32 = 0;
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identifier_w.u32 = 0;
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bytes_cnt = frame->can_dlc;
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bytes_cnt = (bytes_cnt + 3) & ~3;
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bytes_cnt += 16;
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frame_form_w.s.rwcnt = (bytes_cnt >> 2) - 1;
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frame_form_w.s.dlc = can_len2dlc(frame->can_dlc);
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if (frame->can_id & QEMU_CAN_EFF_FLAG) {
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frame_form_w.s.ide = 1;
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identifier_w.s.identifier_base =
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(frame->can_id & 0x1FFC0000) >> 18;
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identifier_w.s.identifier_ext = frame->can_id & 0x3FFFF;
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} else {
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identifier_w.s.identifier_base = frame->can_id & 0x7FF;
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}
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if (frame->flags & QEMU_CAN_FRMF_ESI) {
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frame_form_w.s.esi_rsv = 1;
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}
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if (frame->can_id & QEMU_CAN_RTR_FLAG) {
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frame_form_w.s.rtr = 1;
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}
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if (frame->flags & QEMU_CAN_FRMF_TYPE_FD) { /*CAN FD*/
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frame_form_w.s.fdf = 1;
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if (frame->flags & QEMU_CAN_FRMF_BRS) {
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frame_form_w.s.brs = 1;
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}
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}
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*(uint32_t *)buff = cpu_to_le32(frame_form_w.u32);
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*(uint32_t *)(buff + 4) = cpu_to_le32(identifier_w.u32);
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}
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memcpy(buff + 0x10, frame->data, 0x40);
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return bytes_cnt;
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}
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static void ctucan_update_irq(CtuCanCoreState *s)
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{
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union ctu_can_fd_int_stat int_rq;
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int_rq.u32 = 0;
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if (s->rx_status_rx_settings.s.rxfrc) {
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int_rq.s.rbnei = 1;
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}
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int_rq.u32 &= ~s->int_mask.u32;
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s->int_stat.u32 |= int_rq.u32;
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if (s->int_stat.u32 & s->int_ena.u32) {
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qemu_irq_raise(s->irq);
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} else {
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qemu_irq_lower(s->irq);
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}
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}
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static void ctucan_update_txnf(CtuCanCoreState *s)
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{
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int i;
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int txnf;
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unsigned int buff_st;
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txnf = 0;
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for (i = 0; i < CTUCAN_CORE_TXBUF_NUM; i++) {
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buff_st = (s->tx_status.u32 >> (i * 4)) & 0xf;
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if (buff_st == TXT_ETY) {
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txnf = 1;
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}
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}
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s->status.s.txnf = txnf;
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}
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void ctucan_hardware_reset(CtuCanCoreState *s)
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{
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DPRINTF("Hardware reset in progress!!!\n");
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int i;
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unsigned int buff_st;
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uint32_t buff_st_mask;
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s->tx_status.u32 = 0;
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for (i = 0; i < CTUCAN_CORE_TXBUF_NUM; i++) {
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buff_st_mask = 0xf << (i * 4);
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buff_st = TXT_ETY;
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s->tx_status.u32 = (s->tx_status.u32 & ~buff_st_mask) |
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(buff_st << (i * 4));
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}
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s->status.s.idle = 1;
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ctucan_update_txnf(s);
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s->rx_status_rx_settings.u32 = 0;
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s->rx_tail_pos = 0;
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s->rx_cnt = 0;
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s->rx_frame_rem = 0;
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/* Flush RX buffer */
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s->rx_tail_pos = 0;
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s->rx_cnt = 0;
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s->rx_frame_rem = 0;
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/* Set on progdokum reset value */
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s->mode_settings.u32 = 0;
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s->mode_settings.s.fde = 1;
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s->int_stat.u32 = 0;
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s->int_ena.u32 = 0;
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s->int_mask.u32 = 0;
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s->rx_status_rx_settings.u32 = 0;
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s->rx_status_rx_settings.s.rxe = 0;
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s->rx_fr_ctr.u32 = 0;
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s->tx_fr_ctr.u32 = 0;
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s->yolo_reg.s.yolo_val = 3735928559;
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qemu_irq_lower(s->irq);
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}
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static void ctucan_send_ready_buffers(CtuCanCoreState *s)
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{
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qemu_can_frame frame;
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uint8_t *pf;
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int buff2tx_idx;
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uint32_t tx_prio_max;
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if (!s->mode_settings.s.ena) {
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return;
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}
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do {
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union ctu_can_fd_int_stat int_stat;
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int i;
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buff2tx_idx = -1;
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tx_prio_max = 0;
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for (i = 0; i < CTUCAN_CORE_TXBUF_NUM; i++) {
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uint32_t prio;
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if (extract32(s->tx_status.u32, i * 4, 4) != TXT_RDY) {
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continue;
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}
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prio = (s->tx_priority.u32 >> (i * 4)) & 0x7;
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if (tx_prio_max < prio) {
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tx_prio_max = prio;
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buff2tx_idx = i;
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}
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}
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if (buff2tx_idx == -1) {
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break;
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}
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int_stat.u32 = 0;
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pf = s->tx_buffer[buff2tx_idx].data;
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ctucan_buff2frame(pf, &frame);
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s->status.s.idle = 0;
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s->status.s.txs = 1;
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can_bus_client_send(&s->bus_client, &frame, 1);
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s->status.s.idle = 1;
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s->status.s.txs = 0;
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s->tx_fr_ctr.s.tx_fr_ctr_val++;
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int_stat.s.txi = 1;
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int_stat.s.txbhci = 1;
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s->int_stat.u32 |= int_stat.u32 & ~s->int_mask.u32;
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s->tx_status.u32 = deposit32(s->tx_status.u32,
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buff2tx_idx * 4, 4, TXT_TOK);
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} while (1);
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}
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#define CTUCAN_CORE_TXBUFF_SPAN \
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(CTU_CAN_FD_TXTB2_DATA_1 - CTU_CAN_FD_TXTB1_DATA_1)
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void ctucan_mem_write(CtuCanCoreState *s, hwaddr addr, uint64_t val,
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unsigned size)
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{
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int i;
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DPRINTF("write 0x%02llx addr 0x%02x\n",
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(unsigned long long)val, (unsigned int)addr);
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if (addr >= CTUCAN_CORE_MEM_SIZE) {
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return;
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}
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if (addr >= CTU_CAN_FD_TXTB1_DATA_1) {
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int buff_num;
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addr -= CTU_CAN_FD_TXTB1_DATA_1;
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buff_num = addr / CTUCAN_CORE_TXBUFF_SPAN;
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addr %= CTUCAN_CORE_TXBUFF_SPAN;
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if ((buff_num < CTUCAN_CORE_TXBUF_NUM) &&
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((addr + size) <= sizeof(s->tx_buffer[buff_num].data))) {
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stn_le_p(s->tx_buffer[buff_num].data + addr, size, val);
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}
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} else {
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switch (addr & ~3) {
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case CTU_CAN_FD_MODE:
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s->mode_settings.u32 = (uint32_t)val;
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if (s->mode_settings.s.rst) {
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ctucan_hardware_reset(s);
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s->mode_settings.s.rst = 0;
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}
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break;
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case CTU_CAN_FD_COMMAND:
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{
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union ctu_can_fd_command command;
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command.u32 = (uint32_t)val;
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if (command.s.cdo) {
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s->status.s.dor = 0;
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}
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if (command.s.rrb) {
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s->rx_tail_pos = 0;
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s->rx_cnt = 0;
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s->rx_frame_rem = 0;
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s->rx_status_rx_settings.s.rxfrc = 0;
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}
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if (command.s.txfcrst) {
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s->tx_fr_ctr.s.tx_fr_ctr_val = 0;
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}
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if (command.s.rxfcrst) {
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s->rx_fr_ctr.s.rx_fr_ctr_val = 0;
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}
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break;
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}
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case CTU_CAN_FD_INT_STAT:
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s->int_stat.u32 &= ~(uint32_t)val;
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break;
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case CTU_CAN_FD_INT_ENA_SET:
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s->int_ena.u32 |= (uint32_t)val;
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break;
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case CTU_CAN_FD_INT_ENA_CLR:
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s->int_ena.u32 &= ~(uint32_t)val;
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break;
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case CTU_CAN_FD_INT_MASK_SET:
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s->int_mask.u32 |= (uint32_t)val;
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break;
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case CTU_CAN_FD_INT_MASK_CLR:
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s->int_mask.u32 &= ~(uint32_t)val;
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break;
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case CTU_CAN_FD_TX_COMMAND:
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if (s->mode_settings.s.ena) {
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union ctu_can_fd_tx_command tx_command;
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union ctu_can_fd_tx_command mask;
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unsigned int buff_st;
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uint32_t buff_st_mask;
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tx_command.u32 = (uint32_t)val;
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mask.u32 = 0;
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mask.s.txb1 = 1;
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for (i = 0; i < CTUCAN_CORE_TXBUF_NUM; i++) {
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if (!(tx_command.u32 & (mask.u32 << i))) {
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continue;
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}
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buff_st_mask = 0xf << (i * 4);
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buff_st = (s->tx_status.u32 >> (i * 4)) & 0xf;
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if (tx_command.s.txca) {
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if (buff_st == TXT_RDY) {
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buff_st = TXT_ABT;
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}
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}
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if (tx_command.s.txcr) {
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if ((buff_st == TXT_TOK) || (buff_st == TXT_ERR) ||
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(buff_st == TXT_ABT) || (buff_st == TXT_ETY))
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buff_st = TXT_RDY;
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}
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if (tx_command.s.txce) {
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if ((buff_st == TXT_TOK) || (buff_st == TXT_ERR) ||
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(buff_st == TXT_ABT))
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buff_st = TXT_ETY;
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}
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s->tx_status.u32 = (s->tx_status.u32 & ~buff_st_mask) |
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(buff_st << (i * 4));
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}
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ctucan_send_ready_buffers(s);
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ctucan_update_txnf(s);
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}
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break;
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case CTU_CAN_FD_TX_PRIORITY:
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s->tx_priority.u32 = (uint32_t)val;
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break;
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}
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ctucan_update_irq(s);
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}
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return;
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}
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uint64_t ctucan_mem_read(CtuCanCoreState *s, hwaddr addr, unsigned size)
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{
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uint32_t val = 0;
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DPRINTF("read addr 0x%02x ...\n", (unsigned int)addr);
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if (addr > CTUCAN_CORE_MEM_SIZE) {
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return 0;
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}
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switch (addr & ~3) {
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case CTU_CAN_FD_DEVICE_ID:
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{
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union ctu_can_fd_device_id_version idver;
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idver.u32 = 0;
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idver.s.device_id = CTU_CAN_FD_ID;
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idver.s.ver_major = 2;
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idver.s.ver_minor = 2;
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val = idver.u32;
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}
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break;
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case CTU_CAN_FD_MODE:
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val = s->mode_settings.u32;
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break;
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case CTU_CAN_FD_STATUS:
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val = s->status.u32;
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break;
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case CTU_CAN_FD_INT_STAT:
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val = s->int_stat.u32;
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break;
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case CTU_CAN_FD_INT_ENA_SET:
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case CTU_CAN_FD_INT_ENA_CLR:
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val = s->int_ena.u32;
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break;
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case CTU_CAN_FD_INT_MASK_SET:
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case CTU_CAN_FD_INT_MASK_CLR:
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val = s->int_mask.u32;
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break;
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case CTU_CAN_FD_RX_MEM_INFO:
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s->rx_mem_info.u32 = 0;
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s->rx_mem_info.s.rx_buff_size = CTUCAN_RCV_BUF_LEN >> 2;
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s->rx_mem_info.s.rx_mem_free = (CTUCAN_RCV_BUF_LEN -
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s->rx_cnt) >> 2;
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val = s->rx_mem_info.u32;
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break;
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case CTU_CAN_FD_RX_POINTERS:
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{
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uint32_t rx_head_pos = s->rx_tail_pos + s->rx_cnt;
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rx_head_pos %= CTUCAN_RCV_BUF_LEN;
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s->rx_pointers.s.rx_wpp = rx_head_pos;
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s->rx_pointers.s.rx_rpp = s->rx_tail_pos;
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val = s->rx_pointers.u32;
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break;
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}
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case CTU_CAN_FD_RX_STATUS:
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case CTU_CAN_FD_RX_SETTINGS:
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if (!s->rx_status_rx_settings.s.rxfrc) {
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s->rx_status_rx_settings.s.rxe = 1;
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} else {
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s->rx_status_rx_settings.s.rxe = 0;
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}
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if (((s->rx_cnt + 3) & ~3) == CTUCAN_RCV_BUF_LEN) {
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s->rx_status_rx_settings.s.rxf = 1;
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} else {
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s->rx_status_rx_settings.s.rxf = 0;
|
|
}
|
|
val = s->rx_status_rx_settings.u32;
|
|
break;
|
|
case CTU_CAN_FD_RX_DATA:
|
|
if (s->rx_cnt) {
|
|
memcpy(&val, s->rx_buff + s->rx_tail_pos, 4);
|
|
val = le32_to_cpu(val);
|
|
if (!s->rx_frame_rem) {
|
|
union ctu_can_fd_frame_form_w frame_form_w;
|
|
frame_form_w.u32 = val;
|
|
s->rx_frame_rem = frame_form_w.s.rwcnt * 4 + 4;
|
|
}
|
|
s->rx_cnt -= 4;
|
|
s->rx_frame_rem -= 4;
|
|
if (!s->rx_frame_rem) {
|
|
s->rx_status_rx_settings.s.rxfrc--;
|
|
if (!s->rx_status_rx_settings.s.rxfrc) {
|
|
s->status.s.rxne = 0;
|
|
s->status.s.idle = 1;
|
|
s->status.s.rxs = 0;
|
|
}
|
|
}
|
|
s->rx_tail_pos = (s->rx_tail_pos + 4) % CTUCAN_RCV_BUF_LEN;
|
|
} else {
|
|
val = 0;
|
|
}
|
|
break;
|
|
case CTU_CAN_FD_TX_STATUS:
|
|
val = s->tx_status.u32;
|
|
break;
|
|
case CTU_CAN_FD_TX_PRIORITY:
|
|
val = s->tx_priority.u32;
|
|
break;
|
|
case CTU_CAN_FD_RX_FR_CTR:
|
|
val = s->rx_fr_ctr.s.rx_fr_ctr_val;
|
|
break;
|
|
case CTU_CAN_FD_TX_FR_CTR:
|
|
val = s->tx_fr_ctr.s.tx_fr_ctr_val;
|
|
break;
|
|
case CTU_CAN_FD_YOLO_REG:
|
|
val = s->yolo_reg.s.yolo_val;
|
|
break;
|
|
}
|
|
|
|
val >>= ((addr & 3) << 3);
|
|
if (size < 8) {
|
|
val &= ((uint64_t)1 << (size << 3)) - 1;
|
|
}
|
|
|
|
return val;
|
|
}
|
|
|
|
bool ctucan_can_receive(CanBusClientState *client)
|
|
{
|
|
CtuCanCoreState *s = container_of(client, CtuCanCoreState, bus_client);
|
|
|
|
if (!s->mode_settings.s.ena) {
|
|
return false;
|
|
}
|
|
|
|
return true; /* always return true, when operation mode */
|
|
}
|
|
|
|
ssize_t ctucan_receive(CanBusClientState *client, const qemu_can_frame *frames,
|
|
size_t frames_cnt)
|
|
{
|
|
CtuCanCoreState *s = container_of(client, CtuCanCoreState, bus_client);
|
|
static uint8_t rcv[CTUCAN_MSG_MAX_LEN];
|
|
int i;
|
|
int ret = -1;
|
|
const qemu_can_frame *frame = frames;
|
|
union ctu_can_fd_int_stat int_stat;
|
|
int_stat.u32 = 0;
|
|
|
|
if (frames_cnt <= 0) {
|
|
return 0;
|
|
}
|
|
|
|
ret = ctucan_frame2buff(frame, rcv);
|
|
|
|
if (s->rx_cnt + ret > CTUCAN_RCV_BUF_LEN) { /* Data overrun. */
|
|
s->status.s.dor = 1;
|
|
int_stat.s.doi = 1;
|
|
s->int_stat.u32 |= int_stat.u32 & ~s->int_mask.u32;
|
|
ctucan_update_irq(s);
|
|
DPRINTF("Receive FIFO overrun\n");
|
|
return ret;
|
|
}
|
|
s->status.s.idle = 0;
|
|
s->status.s.rxs = 1;
|
|
int_stat.s.rxi = 1;
|
|
if (((s->rx_cnt + 3) & ~3) == CTUCAN_RCV_BUF_LEN) {
|
|
int_stat.s.rxfi = 1;
|
|
}
|
|
s->int_stat.u32 |= int_stat.u32 & ~s->int_mask.u32;
|
|
s->rx_fr_ctr.s.rx_fr_ctr_val++;
|
|
s->rx_status_rx_settings.s.rxfrc++;
|
|
for (i = 0; i < ret; i++) {
|
|
s->rx_buff[(s->rx_tail_pos + s->rx_cnt) % CTUCAN_RCV_BUF_LEN] = rcv[i];
|
|
s->rx_cnt++;
|
|
}
|
|
s->status.s.rxne = 1;
|
|
|
|
ctucan_update_irq(s);
|
|
|
|
return 1;
|
|
}
|
|
|
|
static CanBusClientInfo ctucan_bus_client_info = {
|
|
.can_receive = ctucan_can_receive,
|
|
.receive = ctucan_receive,
|
|
};
|
|
|
|
|
|
int ctucan_connect_to_bus(CtuCanCoreState *s, CanBusState *bus)
|
|
{
|
|
s->bus_client.info = &ctucan_bus_client_info;
|
|
|
|
if (!bus) {
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (can_bus_insert_client(bus, &s->bus_client) < 0) {
|
|
return -1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void ctucan_disconnect(CtuCanCoreState *s)
|
|
{
|
|
can_bus_remove_client(&s->bus_client);
|
|
}
|
|
|
|
int ctucan_init(CtuCanCoreState *s, qemu_irq irq)
|
|
{
|
|
s->irq = irq;
|
|
|
|
qemu_irq_lower(s->irq);
|
|
|
|
ctucan_hardware_reset(s);
|
|
|
|
return 0;
|
|
}
|
|
|
|
const VMStateDescription vmstate_qemu_ctucan_tx_buffer = {
|
|
.name = "qemu_ctucan_tx_buffer",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.minimum_version_id_old = 1,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT8_ARRAY(data, CtuCanCoreMsgBuffer, CTUCAN_CORE_MSG_MAX_LEN),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static int ctucan_post_load(void *opaque, int version_id)
|
|
{
|
|
CtuCanCoreState *s = opaque;
|
|
ctucan_update_irq(s);
|
|
return 0;
|
|
}
|
|
|
|
/* VMState is needed for live migration of QEMU images */
|
|
const VMStateDescription vmstate_ctucan = {
|
|
.name = "ctucan",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.minimum_version_id_old = 1,
|
|
.post_load = ctucan_post_load,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT32(mode_settings.u32, CtuCanCoreState),
|
|
VMSTATE_UINT32(status.u32, CtuCanCoreState),
|
|
VMSTATE_UINT32(int_stat.u32, CtuCanCoreState),
|
|
VMSTATE_UINT32(int_ena.u32, CtuCanCoreState),
|
|
VMSTATE_UINT32(int_mask.u32, CtuCanCoreState),
|
|
VMSTATE_UINT32(brt.u32, CtuCanCoreState),
|
|
VMSTATE_UINT32(brt_fd.u32, CtuCanCoreState),
|
|
VMSTATE_UINT32(ewl_erp_fault_state.u32, CtuCanCoreState),
|
|
VMSTATE_UINT32(rec_tec.u32, CtuCanCoreState),
|
|
VMSTATE_UINT32(err_norm_err_fd.u32, CtuCanCoreState),
|
|
VMSTATE_UINT32(ctr_pres.u32, CtuCanCoreState),
|
|
VMSTATE_UINT32(filter_a_mask.u32, CtuCanCoreState),
|
|
VMSTATE_UINT32(filter_a_val.u32, CtuCanCoreState),
|
|
VMSTATE_UINT32(filter_b_mask.u32, CtuCanCoreState),
|
|
VMSTATE_UINT32(filter_b_val.u32, CtuCanCoreState),
|
|
VMSTATE_UINT32(filter_c_mask.u32, CtuCanCoreState),
|
|
VMSTATE_UINT32(filter_c_val.u32, CtuCanCoreState),
|
|
VMSTATE_UINT32(filter_ran_low.u32, CtuCanCoreState),
|
|
VMSTATE_UINT32(filter_ran_high.u32, CtuCanCoreState),
|
|
VMSTATE_UINT32(filter_control_filter_status.u32, CtuCanCoreState),
|
|
VMSTATE_UINT32(rx_mem_info.u32, CtuCanCoreState),
|
|
VMSTATE_UINT32(rx_pointers.u32, CtuCanCoreState),
|
|
VMSTATE_UINT32(rx_status_rx_settings.u32, CtuCanCoreState),
|
|
VMSTATE_UINT32(tx_status.u32, CtuCanCoreState),
|
|
VMSTATE_UINT32(tx_priority.u32, CtuCanCoreState),
|
|
VMSTATE_UINT32(err_capt_alc.u32, CtuCanCoreState),
|
|
VMSTATE_UINT32(trv_delay_ssp_cfg.u32, CtuCanCoreState),
|
|
VMSTATE_UINT32(rx_fr_ctr.u32, CtuCanCoreState),
|
|
VMSTATE_UINT32(tx_fr_ctr.u32, CtuCanCoreState),
|
|
VMSTATE_UINT32(debug_register.u32, CtuCanCoreState),
|
|
VMSTATE_UINT32(yolo_reg.u32, CtuCanCoreState),
|
|
VMSTATE_UINT32(timestamp_low.u32, CtuCanCoreState),
|
|
VMSTATE_UINT32(timestamp_high.u32, CtuCanCoreState),
|
|
|
|
VMSTATE_STRUCT_ARRAY(tx_buffer, CtuCanCoreState,
|
|
CTUCAN_CORE_TXBUF_NUM, 0, vmstate_qemu_ctucan_tx_buffer,
|
|
CtuCanCoreMsgBuffer),
|
|
|
|
VMSTATE_BUFFER(rx_buff, CtuCanCoreState),
|
|
VMSTATE_UINT32(rx_tail_pos, CtuCanCoreState),
|
|
VMSTATE_UINT32(rx_cnt, CtuCanCoreState),
|
|
VMSTATE_UINT32(rx_frame_rem, CtuCanCoreState),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|