The only way object_property_add() can fail is when a property with the same name already exists. Since our property names are all hardcoded, failure is a programming error, and the appropriate way to handle it is passing &error_abort. Same for its variants, except for object_property_add_child(), which additionally fails when the child already has a parent. Parentage is also under program control, so this is a programming error, too. We have a bit over 500 callers. Almost half of them pass &error_abort, slightly fewer ignore errors, one test case handles errors, and the remaining few callers pass them to their own callers. The previous few commits demonstrated once again that ignoring programming errors is a bad idea. Of the few ones that pass on errors, several violate the Error API. The Error ** argument must be NULL, &error_abort, &error_fatal, or a pointer to a variable containing NULL. Passing an argument of the latter kind twice without clearing it in between is wrong: if the first call sets an error, it no longer points to NULL for the second call. ich9_pm_add_properties(), sparc32_ledma_realize(), sparc32_dma_realize(), xilinx_axidma_realize(), xilinx_enet_realize() are wrong that way. When the one appropriate choice of argument is &error_abort, letting users pick the argument is a bad idea. Drop parameter @errp and assert the preconditions instead. There's one exception to "duplicate property name is a programming error": the way object_property_add() implements the magic (and undocumented) "automatic arrayification". Don't drop @errp there. Instead, rename object_property_add() to object_property_try_add(), and add the obvious wrapper object_property_add(). Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20200505152926.18877-15-armbru@redhat.com> [Two semantic rebase conflicts resolved]
270 lines
9.6 KiB
C
270 lines
9.6 KiB
C
/*
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* SmartFusion2 SoC emulation.
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*
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* Copyright (c) 2017-2020 Subbaraya Sundeep <sundeep.lkml@gmail.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qapi/error.h"
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#include "exec/address-spaces.h"
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#include "hw/char/serial.h"
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#include "hw/irq.h"
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#include "hw/arm/msf2-soc.h"
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#include "hw/misc/unimp.h"
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#include "sysemu/runstate.h"
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#include "sysemu/sysemu.h"
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#define MSF2_TIMER_BASE 0x40004000
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#define MSF2_SYSREG_BASE 0x40038000
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#define MSF2_EMAC_BASE 0x40041000
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#define ENVM_BASE_ADDRESS 0x60000000
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#define SRAM_BASE_ADDRESS 0x20000000
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#define MSF2_EMAC_IRQ 12
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#define MSF2_ENVM_MAX_SIZE (512 * KiB)
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/*
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* eSRAM max size is 80k without SECDED(Single error correction and
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* dual error detection) feature and 64k with SECDED.
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* We do not support SECDED now.
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*/
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#define MSF2_ESRAM_MAX_SIZE (80 * KiB)
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static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 };
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static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 };
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static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
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static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
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static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 };
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static void do_sys_reset(void *opaque, int n, int level)
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{
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if (level) {
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qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
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}
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}
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static void m2sxxx_soc_initfn(Object *obj)
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{
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MSF2State *s = MSF2_SOC(obj);
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int i;
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sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m),
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TYPE_ARMV7M);
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sysbus_init_child_obj(obj, "sysreg", &s->sysreg, sizeof(s->sysreg),
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TYPE_MSF2_SYSREG);
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sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer),
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TYPE_MSS_TIMER);
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for (i = 0; i < MSF2_NUM_SPIS; i++) {
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sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]),
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TYPE_MSS_SPI);
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}
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sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac),
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TYPE_MSS_EMAC);
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if (nd_table[0].used) {
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qemu_check_nic_model(&nd_table[0], TYPE_MSS_EMAC);
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qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
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}
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}
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static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
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{
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MSF2State *s = MSF2_SOC(dev_soc);
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DeviceState *dev, *armv7m;
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SysBusDevice *busdev;
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Error *err = NULL;
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int i;
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MemoryRegion *system_memory = get_system_memory();
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MemoryRegion *nvm = g_new(MemoryRegion, 1);
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MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);
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MemoryRegion *sram = g_new(MemoryRegion, 1);
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memory_region_init_rom(nvm, OBJECT(dev_soc), "MSF2.eNVM", s->envm_size,
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&error_fatal);
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/*
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* On power-on, the eNVM region 0x60000000 is automatically
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* remapped to the Cortex-M3 processor executable region
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* start address (0x0). We do not support remapping other eNVM,
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* eSRAM and DDR regions by guest(via Sysreg) currently.
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*/
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memory_region_init_alias(nvm_alias, OBJECT(dev_soc), "MSF2.eNVM", nvm, 0,
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s->envm_size);
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memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm);
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memory_region_add_subregion(system_memory, 0, nvm_alias);
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memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size,
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&error_fatal);
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memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
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armv7m = DEVICE(&s->armv7m);
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qdev_prop_set_uint32(armv7m, "num-irq", 81);
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qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
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qdev_prop_set_bit(armv7m, "enable-bitband", true);
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object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
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"memory", &error_abort);
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object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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if (!s->m3clk) {
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error_setg(errp, "Invalid m3clk value");
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error_append_hint(errp, "m3clk can not be zero\n");
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return;
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}
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qdev_connect_gpio_out_named(DEVICE(&s->armv7m.nvic), "SYSRESETREQ", 0,
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qemu_allocate_irq(&do_sys_reset, NULL, 0));
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system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk;
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for (i = 0; i < MSF2_NUM_UARTS; i++) {
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if (serial_hd(i)) {
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serial_mm_init(get_system_memory(), uart_addr[i], 2,
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qdev_get_gpio_in(armv7m, uart_irq[i]),
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115200, serial_hd(i), DEVICE_NATIVE_ENDIAN);
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}
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}
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dev = DEVICE(&s->timer);
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/* APB0 clock is the timer input clock */
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qdev_prop_set_uint32(dev, "clock-frequency", s->m3clk / s->apb0div);
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object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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busdev = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);
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sysbus_connect_irq(busdev, 0,
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qdev_get_gpio_in(armv7m, timer_irq[0]));
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sysbus_connect_irq(busdev, 1,
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qdev_get_gpio_in(armv7m, timer_irq[1]));
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dev = DEVICE(&s->sysreg);
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qdev_prop_set_uint32(dev, "apb0divisor", s->apb0div);
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qdev_prop_set_uint32(dev, "apb1divisor", s->apb1div);
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object_property_set_bool(OBJECT(&s->sysreg), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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busdev = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);
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for (i = 0; i < MSF2_NUM_SPIS; i++) {
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gchar *bus_name;
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object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
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qdev_get_gpio_in(armv7m, spi_irq[i]));
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/* Alias controller SPI bus to the SoC itself */
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bus_name = g_strdup_printf("spi%d", i);
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object_property_add_alias(OBJECT(s), bus_name,
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OBJECT(&s->spi[i]), "spi");
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g_free(bus_name);
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}
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dev = DEVICE(&s->emac);
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object_property_set_link(OBJECT(&s->emac), OBJECT(get_system_memory()),
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"ahb-bus", &error_abort);
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object_property_set_bool(OBJECT(&s->emac), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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busdev = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(busdev, 0, MSF2_EMAC_BASE);
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sysbus_connect_irq(busdev, 0,
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qdev_get_gpio_in(armv7m, MSF2_EMAC_IRQ));
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/* Below devices are not modelled yet. */
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create_unimplemented_device("i2c_0", 0x40002000, 0x1000);
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create_unimplemented_device("dma", 0x40003000, 0x1000);
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create_unimplemented_device("watchdog", 0x40005000, 0x1000);
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create_unimplemented_device("i2c_1", 0x40012000, 0x1000);
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create_unimplemented_device("gpio", 0x40013000, 0x1000);
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create_unimplemented_device("hs-dma", 0x40014000, 0x1000);
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create_unimplemented_device("can", 0x40015000, 0x1000);
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create_unimplemented_device("rtc", 0x40017000, 0x1000);
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create_unimplemented_device("apb_config", 0x40020000, 0x10000);
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create_unimplemented_device("usb", 0x40043000, 0x1000);
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}
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static Property m2sxxx_soc_properties[] = {
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/*
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* part name specifies the type of SmartFusion2 device variant(this
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* property is for information purpose only.
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*/
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DEFINE_PROP_STRING("cpu-type", MSF2State, cpu_type),
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DEFINE_PROP_STRING("part-name", MSF2State, part_name),
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DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size, MSF2_ENVM_MAX_SIZE),
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DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size,
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MSF2_ESRAM_MAX_SIZE),
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/* Libero GUI shows 100Mhz as default for clocks */
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DEFINE_PROP_UINT32("m3clk", MSF2State, m3clk, 100 * 1000000),
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/* default divisors in Libero GUI */
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DEFINE_PROP_UINT8("apb0div", MSF2State, apb0div, 2),
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DEFINE_PROP_UINT8("apb1div", MSF2State, apb1div, 2),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void m2sxxx_soc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = m2sxxx_soc_realize;
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device_class_set_props(dc, m2sxxx_soc_properties);
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}
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static const TypeInfo m2sxxx_soc_info = {
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.name = TYPE_MSF2_SOC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(MSF2State),
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.instance_init = m2sxxx_soc_initfn,
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.class_init = m2sxxx_soc_class_init,
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};
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static void m2sxxx_soc_types(void)
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{
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type_register_static(&m2sxxx_soc_info);
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}
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type_init(m2sxxx_soc_types)
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