qemu-patch-raspberry4/hw/riscv
KONRAD Frederic 6fad7d1893
riscv: htif: increase the priority of the htif subregion
The htif device is supposed to be mapped over an other subregion. So increase
its priority to one to avoid any conflict.

Here is the output of info mtree:

Before:
(qemu) info mtree
 address-space: memory
   0000000000000000-ffffffffffffffff (prio 0, i/o): system
     0000000000000000-000000000000000f (prio 0, i/o): riscv.htif.uart
     0000000000000000-0000000000011fff (prio 0, ram): riscv.spike.bootrom
     0000000002000000-000000000200ffff (prio 0, i/o): riscv.sifive.clint
     0000000080000000-0000000087ffffff (prio 0, ram): riscv.spike.ram

 address-space: I/O
   0000000000000000-000000000000ffff (prio 0, i/o): io

 address-space: cpu-memory-0
   0000000000000000-ffffffffffffffff (prio 0, i/o): system
     0000000000000000-000000000000000f (prio 0, i/o): riscv.htif.uart
     0000000000000000-0000000000011fff (prio 0, ram): riscv.spike.bootrom
     0000000002000000-000000000200ffff (prio 0, i/o): riscv.sifive.clint
     0000000080000000-0000000087ffffff (prio 0, ram): riscv.spike.ram

After:
 (qemu) info mtree
 address-space: memory
   0000000000000000-ffffffffffffffff (prio 0, i/o): system
     0000000000000000-000000000000000f (prio 1, i/o): riscv.htif.uart
     0000000000000000-0000000000011fff (prio 0, ram): riscv.spike.bootrom
     0000000002000000-000000000200ffff (prio 0, i/o): riscv.sifive.clint
     0000000080000000-0000000087ffffff (prio 0, ram): riscv.spike.ram

 address-space: I/O
   0000000000000000-000000000000ffff (prio 0, i/o): io

 address-space: cpu-memory-0
   0000000000000000-ffffffffffffffff (prio 0, i/o): system
     0000000000000000-000000000000000f (prio 1, i/o): riscv.htif.uart
     0000000000000000-0000000000011fff (prio 0, ram): riscv.spike.bootrom
     0000000002000000-000000000200ffff (prio 0, i/o): riscv.sifive.clint
     0000000080000000-0000000087ffffff (prio 0, ram): riscv.spike.ram

Reviewed-by: Michael Clark <mjc@sifive.com>
Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
Signed-off-by: Michael Clark <mjc@sifive.com>

Message-Id: <1525360636-18229-3-git-send-email-frederic.konrad@adacore.com>
2018-05-09 07:57:46 +12:00
..
Makefile.objs RISC-V Build Infrastructure 2018-03-07 08:30:28 +13:00
riscv_hart.c RISC-V HART Array 2018-03-07 08:30:28 +13:00
riscv_htif.c riscv: htif: increase the priority of the htif subregion 2018-05-09 07:57:46 +12:00
sifive_clint.c SiFive RISC-V CLINT Block 2018-03-07 08:30:28 +13:00
sifive_e.c Change references to serial_hds[] to serial_hd() 2018-04-26 13:57:00 +01:00
sifive_plic.c SiFive RISC-V PLIC Block 2018-03-07 08:30:28 +13:00
sifive_prci.c SiFive RISC-V PRCI Block 2018-03-07 08:30:28 +13:00
sifive_test.c SiFive RISC-V Test Finisher 2018-03-07 08:30:28 +13:00
sifive_u.c Change references to serial_hds[] to serial_hd() 2018-04-26 13:57:00 +01:00
sifive_uart.c SiFive RISC-V UART Device 2018-03-07 08:30:28 +13:00
spike.c Change references to serial_hds[] to serial_hd() 2018-04-26 13:57:00 +01:00
virt.c Change references to serial_hds[] to serial_hd() 2018-04-26 13:57:00 +01:00