8f4efc5588
sparc64 timer has tick counter which can be set and read, and tick compare value used as deadline to fire timer interrupt. The timer is not used as periodic timer, instead deadline is set each time new timer interrupt is needed. v3 -> v4: - coding style v2 -> v3: - added missing timer debug output macro - CPUTimer struct and typedef moved to cpu.h - change CPU_SAVE_VERSION to 6, older save formats not supported v1 -> v2: - new conversion helpers cpu_to_timer_ticks and timer_to_cpu_ticks - save offset from clock source to implement cpu_tick_set_count - renamed struct sun4u_timer to CPUTimer - load and save cpu timers v0 -> v1: - coding style Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
200 lines
6 KiB
C
200 lines
6 KiB
C
#include "hw/hw.h"
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#include "hw/boards.h"
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#include "qemu-timer.h"
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#include "exec-all.h"
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void cpu_save(QEMUFile *f, void *opaque)
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{
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CPUState *env = opaque;
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int i;
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uint32_t tmp;
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// if env->cwp == env->nwindows - 1, this will set the ins of the last
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// window as the outs of the first window
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cpu_set_cwp(env, env->cwp);
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for(i = 0; i < 8; i++)
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qemu_put_betls(f, &env->gregs[i]);
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qemu_put_be32s(f, &env->nwindows);
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for(i = 0; i < env->nwindows * 16; i++)
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qemu_put_betls(f, &env->regbase[i]);
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/* FPU */
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for(i = 0; i < TARGET_FPREGS; i++) {
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union {
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float32 f;
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uint32_t i;
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} u;
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u.f = env->fpr[i];
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qemu_put_be32(f, u.i);
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}
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qemu_put_betls(f, &env->pc);
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qemu_put_betls(f, &env->npc);
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qemu_put_betls(f, &env->y);
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tmp = GET_PSR(env);
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qemu_put_be32(f, tmp);
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qemu_put_betls(f, &env->fsr);
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qemu_put_betls(f, &env->tbr);
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tmp = env->interrupt_index;
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qemu_put_be32(f, tmp);
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qemu_put_be32s(f, &env->pil_in);
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#ifndef TARGET_SPARC64
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qemu_put_be32s(f, &env->wim);
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/* MMU */
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for (i = 0; i < 32; i++)
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qemu_put_be32s(f, &env->mmuregs[i]);
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#else
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qemu_put_be64s(f, &env->lsu);
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for (i = 0; i < 16; i++) {
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qemu_put_be64s(f, &env->immuregs[i]);
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qemu_put_be64s(f, &env->dmmuregs[i]);
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}
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for (i = 0; i < 64; i++) {
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qemu_put_be64s(f, &env->itlb[i].tag);
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qemu_put_be64s(f, &env->itlb[i].tte);
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qemu_put_be64s(f, &env->dtlb[i].tag);
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qemu_put_be64s(f, &env->dtlb[i].tte);
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}
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qemu_put_be32s(f, &env->mmu_version);
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for (i = 0; i < MAXTL_MAX; i++) {
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qemu_put_be64s(f, &env->ts[i].tpc);
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qemu_put_be64s(f, &env->ts[i].tnpc);
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qemu_put_be64s(f, &env->ts[i].tstate);
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qemu_put_be32s(f, &env->ts[i].tt);
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}
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qemu_put_be32s(f, &env->xcc);
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qemu_put_be32s(f, &env->asi);
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qemu_put_be32s(f, &env->pstate);
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qemu_put_be32s(f, &env->tl);
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qemu_put_be32s(f, &env->cansave);
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qemu_put_be32s(f, &env->canrestore);
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qemu_put_be32s(f, &env->otherwin);
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qemu_put_be32s(f, &env->wstate);
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qemu_put_be32s(f, &env->cleanwin);
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for (i = 0; i < 8; i++)
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qemu_put_be64s(f, &env->agregs[i]);
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for (i = 0; i < 8; i++)
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qemu_put_be64s(f, &env->bgregs[i]);
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for (i = 0; i < 8; i++)
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qemu_put_be64s(f, &env->igregs[i]);
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for (i = 0; i < 8; i++)
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qemu_put_be64s(f, &env->mgregs[i]);
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qemu_put_be64s(f, &env->fprs);
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qemu_put_be64s(f, &env->tick_cmpr);
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qemu_put_be64s(f, &env->stick_cmpr);
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cpu_put_timer(f, env->tick);
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cpu_put_timer(f, env->stick);
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qemu_put_be64s(f, &env->gsr);
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qemu_put_be32s(f, &env->gl);
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qemu_put_be64s(f, &env->hpstate);
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for (i = 0; i < MAXTL_MAX; i++)
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qemu_put_be64s(f, &env->htstate[i]);
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qemu_put_be64s(f, &env->hintp);
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qemu_put_be64s(f, &env->htba);
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qemu_put_be64s(f, &env->hver);
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qemu_put_be64s(f, &env->hstick_cmpr);
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qemu_put_be64s(f, &env->ssr);
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cpu_put_timer(f, env->hstick);
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#endif
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}
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int cpu_load(QEMUFile *f, void *opaque, int version_id)
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{
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CPUState *env = opaque;
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int i;
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uint32_t tmp;
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if (version_id < 6)
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return -EINVAL;
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for(i = 0; i < 8; i++)
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qemu_get_betls(f, &env->gregs[i]);
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qemu_get_be32s(f, &env->nwindows);
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for(i = 0; i < env->nwindows * 16; i++)
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qemu_get_betls(f, &env->regbase[i]);
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/* FPU */
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for(i = 0; i < TARGET_FPREGS; i++) {
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union {
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float32 f;
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uint32_t i;
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} u;
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u.i = qemu_get_be32(f);
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env->fpr[i] = u.f;
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}
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qemu_get_betls(f, &env->pc);
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qemu_get_betls(f, &env->npc);
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qemu_get_betls(f, &env->y);
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tmp = qemu_get_be32(f);
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env->cwp = 0; /* needed to ensure that the wrapping registers are
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correctly updated */
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PUT_PSR(env, tmp);
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qemu_get_betls(f, &env->fsr);
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qemu_get_betls(f, &env->tbr);
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tmp = qemu_get_be32(f);
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env->interrupt_index = tmp;
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qemu_get_be32s(f, &env->pil_in);
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#ifndef TARGET_SPARC64
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qemu_get_be32s(f, &env->wim);
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/* MMU */
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for (i = 0; i < 32; i++)
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qemu_get_be32s(f, &env->mmuregs[i]);
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#else
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qemu_get_be64s(f, &env->lsu);
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for (i = 0; i < 16; i++) {
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qemu_get_be64s(f, &env->immuregs[i]);
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qemu_get_be64s(f, &env->dmmuregs[i]);
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}
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for (i = 0; i < 64; i++) {
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qemu_get_be64s(f, &env->itlb[i].tag);
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qemu_get_be64s(f, &env->itlb[i].tte);
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qemu_get_be64s(f, &env->dtlb[i].tag);
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qemu_get_be64s(f, &env->dtlb[i].tte);
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}
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qemu_get_be32s(f, &env->mmu_version);
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for (i = 0; i < MAXTL_MAX; i++) {
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qemu_get_be64s(f, &env->ts[i].tpc);
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qemu_get_be64s(f, &env->ts[i].tnpc);
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qemu_get_be64s(f, &env->ts[i].tstate);
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qemu_get_be32s(f, &env->ts[i].tt);
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}
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qemu_get_be32s(f, &env->xcc);
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qemu_get_be32s(f, &env->asi);
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qemu_get_be32s(f, &env->pstate);
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qemu_get_be32s(f, &env->tl);
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qemu_get_be32s(f, &env->cansave);
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qemu_get_be32s(f, &env->canrestore);
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qemu_get_be32s(f, &env->otherwin);
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qemu_get_be32s(f, &env->wstate);
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qemu_get_be32s(f, &env->cleanwin);
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for (i = 0; i < 8; i++)
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qemu_get_be64s(f, &env->agregs[i]);
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for (i = 0; i < 8; i++)
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qemu_get_be64s(f, &env->bgregs[i]);
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for (i = 0; i < 8; i++)
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qemu_get_be64s(f, &env->igregs[i]);
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for (i = 0; i < 8; i++)
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qemu_get_be64s(f, &env->mgregs[i]);
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qemu_get_be64s(f, &env->fprs);
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qemu_get_be64s(f, &env->tick_cmpr);
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qemu_get_be64s(f, &env->stick_cmpr);
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cpu_get_timer(f, env->tick);
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cpu_get_timer(f, env->stick);
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qemu_get_be64s(f, &env->gsr);
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qemu_get_be32s(f, &env->gl);
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qemu_get_be64s(f, &env->hpstate);
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for (i = 0; i < MAXTL_MAX; i++)
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qemu_get_be64s(f, &env->htstate[i]);
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qemu_get_be64s(f, &env->hintp);
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qemu_get_be64s(f, &env->htba);
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qemu_get_be64s(f, &env->hver);
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qemu_get_be64s(f, &env->hstick_cmpr);
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qemu_get_be64s(f, &env->ssr);
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cpu_get_timer(f, env->hstick);
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#endif
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tlb_flush(env, 1);
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return 0;
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}
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