We extend RISC-V spike machine to allow creating a multi-socket machine. Each RISC-V spike machine socket is a NUMA node having a set of HARTs, a memory instance, and a CLINT instance. Other devices are shared between all sockets. We also update the generated device tree accordingly. By default, NUMA multi-socket support is disabled for RISC-V spike machine. To enable it, users can use "-numa" command-line options of QEMU. Example1: For two NUMA nodes with 2 CPUs each, append following to command-line options: "-smp 4 -numa node -numa node" Example2: For two NUMA nodes with 1 and 3 CPUs, append following to command-line options: "-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \ -numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \ -numa cpu,node-id=1,core-id=3" The maximum number of sockets in a RISC-V spike machine is 8 but this limit can be changed in future. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Message-Id: <20200616032229.766089-5-anup.patel@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
335 lines
13 KiB
C
335 lines
13 KiB
C
/*
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* QEMU RISC-V Spike Board
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2017-2018 SiFive, Inc.
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*
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* This provides a RISC-V Board with the following devices:
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*
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* 0) HTIF Console and Poweroff
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* 1) CLINT (Timer and IPI)
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* 2) PLIC (Platform Level Interrupt Controller)
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "hw/boards.h"
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#include "hw/loader.h"
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#include "hw/sysbus.h"
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#include "target/riscv/cpu.h"
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#include "hw/riscv/riscv_htif.h"
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#include "hw/riscv/riscv_hart.h"
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#include "hw/riscv/sifive_clint.h"
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#include "hw/riscv/spike.h"
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#include "hw/riscv/boot.h"
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#include "hw/riscv/numa.h"
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#include "chardev/char.h"
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#include "sysemu/arch_init.h"
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#include "sysemu/device_tree.h"
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#include "sysemu/qtest.h"
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#include "sysemu/sysemu.h"
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/*
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* Not like other RISC-V machines that use plain binary bios images,
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* keeping ELF files here was intentional because BIN files don't work
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* for the Spike machine as HTIF emulation depends on ELF parsing.
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*/
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#if defined(TARGET_RISCV32)
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# define BIOS_FILENAME "opensbi-riscv32-generic-fw_dynamic.elf"
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#else
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# define BIOS_FILENAME "opensbi-riscv64-generic-fw_dynamic.elf"
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#endif
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static const struct MemmapEntry {
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hwaddr base;
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hwaddr size;
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} spike_memmap[] = {
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[SPIKE_MROM] = { 0x1000, 0xf000 },
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[SPIKE_CLINT] = { 0x2000000, 0x10000 },
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[SPIKE_DRAM] = { 0x80000000, 0x0 },
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};
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static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
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uint64_t mem_size, const char *cmdline)
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{
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void *fdt;
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uint64_t addr, size;
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unsigned long clint_addr;
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int cpu, socket;
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MachineState *mc = MACHINE(s);
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uint32_t *clint_cells;
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uint32_t cpu_phandle, intc_phandle, phandle = 1;
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char *name, *mem_name, *clint_name, *clust_name;
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char *core_name, *cpu_name, *intc_name;
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fdt = s->fdt = create_device_tree(&s->fdt_size);
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if (!fdt) {
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error_report("create_device_tree() failed");
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exit(1);
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}
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qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");
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qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev");
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qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
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qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
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qemu_fdt_add_subnode(fdt, "/htif");
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qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0");
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qemu_fdt_add_subnode(fdt, "/soc");
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qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
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qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
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qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
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qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
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qemu_fdt_add_subnode(fdt, "/cpus");
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qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
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SIFIVE_CLINT_TIMEBASE_FREQ);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
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qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
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for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
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clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
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qemu_fdt_add_subnode(fdt, clust_name);
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clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
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for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
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cpu_phandle = phandle++;
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cpu_name = g_strdup_printf("/cpus/cpu@%d",
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s->soc[socket].hartid_base + cpu);
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qemu_fdt_add_subnode(fdt, cpu_name);
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#if defined(TARGET_RISCV32)
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qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32");
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#else
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qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48");
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#endif
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name = riscv_isa_string(&s->soc[socket].harts[cpu]);
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qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name);
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g_free(name);
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qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv");
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qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay");
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qemu_fdt_setprop_cell(fdt, cpu_name, "reg",
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s->soc[socket].hartid_base + cpu);
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qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
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riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket);
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qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle);
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intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
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qemu_fdt_add_subnode(fdt, intc_name);
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intc_phandle = phandle++;
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qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle);
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qemu_fdt_setprop_string(fdt, intc_name, "compatible",
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"riscv,cpu-intc");
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qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0);
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qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1);
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clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
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clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
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clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
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clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
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core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
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qemu_fdt_add_subnode(fdt, core_name);
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qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle);
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g_free(core_name);
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g_free(intc_name);
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g_free(cpu_name);
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}
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addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(mc, socket);
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size = riscv_socket_mem_size(mc, socket);
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mem_name = g_strdup_printf("/memory@%lx", (long)addr);
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qemu_fdt_add_subnode(fdt, mem_name);
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qemu_fdt_setprop_cells(fdt, mem_name, "reg",
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addr >> 32, addr, size >> 32, size);
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qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory");
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riscv_socket_fdt_write_id(mc, fdt, mem_name, socket);
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g_free(mem_name);
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clint_addr = memmap[SPIKE_CLINT].base +
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(memmap[SPIKE_CLINT].size * socket);
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clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
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qemu_fdt_add_subnode(fdt, clint_name);
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qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0");
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qemu_fdt_setprop_cells(fdt, clint_name, "reg",
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0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size);
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qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
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clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
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riscv_socket_fdt_write_id(mc, fdt, clint_name, socket);
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g_free(clint_name);
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g_free(clint_cells);
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g_free(clust_name);
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}
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riscv_socket_fdt_write_distance_matrix(mc, fdt);
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if (cmdline) {
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qemu_fdt_add_subnode(fdt, "/chosen");
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qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
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}
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}
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static void spike_board_init(MachineState *machine)
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{
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const struct MemmapEntry *memmap = spike_memmap;
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SpikeState *s = SPIKE_MACHINE(machine);
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MemoryRegion *system_memory = get_system_memory();
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MemoryRegion *main_mem = g_new(MemoryRegion, 1);
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MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
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uint32_t fdt_load_addr;
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uint64_t kernel_entry;
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char *soc_name;
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int i, base_hartid, hart_count;
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/* Check socket count limit */
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if (SPIKE_SOCKETS_MAX < riscv_socket_count(machine)) {
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error_report("number of sockets/nodes should be less than %d",
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SPIKE_SOCKETS_MAX);
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exit(1);
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}
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/* Initialize sockets */
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for (i = 0; i < riscv_socket_count(machine); i++) {
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if (!riscv_socket_check_hartids(machine, i)) {
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error_report("discontinuous hartids in socket%d", i);
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exit(1);
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}
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base_hartid = riscv_socket_first_hartid(machine, i);
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if (base_hartid < 0) {
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error_report("can't find hartid base for socket%d", i);
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exit(1);
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}
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hart_count = riscv_socket_hart_count(machine, i);
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if (hart_count < 0) {
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error_report("can't find hart count for socket%d", i);
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exit(1);
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}
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soc_name = g_strdup_printf("soc%d", i);
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object_initialize_child(OBJECT(machine), soc_name, &s->soc[i],
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TYPE_RISCV_HART_ARRAY);
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g_free(soc_name);
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object_property_set_str(OBJECT(&s->soc[i]), "cpu-type",
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machine->cpu_type, &error_abort);
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object_property_set_int(OBJECT(&s->soc[i]), "hartid-base",
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base_hartid, &error_abort);
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object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
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hart_count, &error_abort);
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sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
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/* Core Local Interruptor (timer and IPI) for each socket */
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sifive_clint_create(
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memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size,
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memmap[SPIKE_CLINT].size, base_hartid, hart_count,
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SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
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}
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/* register system main memory (actual RAM) */
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memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
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machine->ram_size, &error_fatal);
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memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
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main_mem);
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/* create device tree */
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create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
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/* boot rom */
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memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
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memmap[SPIKE_MROM].size, &error_fatal);
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memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
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mask_rom);
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riscv_find_and_load_firmware(machine, BIOS_FILENAME,
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memmap[SPIKE_DRAM].base,
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htif_symbol_callback);
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if (machine->kernel_filename) {
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kernel_entry = riscv_load_kernel(machine->kernel_filename,
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htif_symbol_callback);
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if (machine->initrd_filename) {
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hwaddr start;
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hwaddr end = riscv_load_initrd(machine->initrd_filename,
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machine->ram_size, kernel_entry,
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&start);
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qemu_fdt_setprop_cell(s->fdt, "/chosen",
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"linux,initrd-start", start);
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qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
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end);
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}
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} else {
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/*
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* If dynamic firmware is used, it doesn't know where is the next mode
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* if kernel argument is not set.
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*/
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kernel_entry = 0;
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}
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/* Compute the fdt load address in dram */
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fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
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machine->ram_size, s->fdt);
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/* load the reset vector */
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riscv_setup_rom_reset_vec(memmap[SPIKE_DRAM].base, memmap[SPIKE_MROM].base,
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memmap[SPIKE_MROM].size, kernel_entry,
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fdt_load_addr, s->fdt);
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/* initialize HTIF using symbols found in load_kernel */
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htif_mm_init(system_memory, mask_rom,
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&s->soc[0].harts[0].env, serial_hd(0));
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}
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static void spike_machine_instance_init(Object *obj)
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{
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}
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static void spike_machine_class_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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mc->desc = "RISC-V Spike board";
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mc->init = spike_board_init;
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mc->max_cpus = SPIKE_CPUS_MAX;
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mc->is_default = true;
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mc->default_cpu_type = SPIKE_V1_10_0_CPU;
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mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
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mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
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mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
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mc->numa_mem_supported = true;
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}
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static const TypeInfo spike_machine_typeinfo = {
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.name = MACHINE_TYPE_NAME("spike"),
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.parent = TYPE_MACHINE,
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.class_init = spike_machine_class_init,
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.instance_init = spike_machine_instance_init,
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.instance_size = sizeof(SpikeState),
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};
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static void spike_machine_init_register_types(void)
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{
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type_register_static(&spike_machine_typeinfo);
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}
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type_init(spike_machine_init_register_types)
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