The processor stop status and control register (PSSCR) is used to
control the power saving facilities of the thread. The exit criterion
bit (EC) is used to specify whether the thread should be woken by any
interrupt (EC == 0) or only an interrupt enabled in the LPCR to wake the
thread (EC == 1).
The rtas facilities start-cpu and self-stop are used to transition a
vcpu between the stopped and running states. When a vcpu is stopped it
may only be started again by the start-cpu rtas call.
Currently a vcpu in the stopped state will start again whenever an
interrupt comes along due to PSSCR_EC being cleared, and while this is
architecturally correct for a hardware thread, a vcpu is expected to
only be woken by calling start-cpu. This means when performing a reboot
on a tcg machine that the secondary threads will restart while the
primary is still in slof, this is unsupported and causes call traces
like:
SLOF **********************************************************************
QEMU Starting
Build Date = Jan 14 2019 18:00:39
FW Version = git-a5b428e1c1eae703
Press "s" to enter Open Firmware.
qemu: fatal: Trying to deliver HV exception (MSR) 70 with no HV support
NIP 6d61676963313230 LR 000000003dbe0308 CTR 6d61676963313233 XER 0000000000000000 CPU#1
MSR 0000000000000000 HID0 0000000000000000 HF 0000000000000000 iidx 3 didx 3
TB 00000026 115746031956 DECR 18446744073326238463
GPR00 000000003dbe0308 000000003e669fe0 000000003dc10700 0000000000000003
GPR04 000000003dc62198 000000003dc62178 000000003dc0ea48 0000000000000030
GPR08 000000003dc621a8 0000000000000018 000000003e466008 000000003dc50700
GPR12 c00000000093a4e0 c00000003ffff300 c00000003e533f90 0000000000000000
GPR16 0000000000000000 0000000000000000 000000003e466010 000000003dc0b040
GPR20 0000000000008000 000000000000f003 0000000000000006 000000003e66a050
GPR24 000000003dc06400 000000003dc0ae70 0000000000000003 000000000000f001
GPR28 000000003e66a060 ffffffffffffffff 6d61676963313233 0000000000000028
CR 28000222 [ E L - - - E E E ] RES ffffffffffffffff
FPR00 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR04 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR08 0000000000000000 0000000000000000 0000000000000000 00000000311825e0
FPR12 00000000311825e0 0000000000000000 0000000000000000 0000000000000000
FPR16 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR20 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR24 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR28 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPSCR 0000000000000000
SRR0 000000003dbe06b0 SRR1 0000000000080000 PVR 00000000004e1200 VRSAVE 0000000000000000
SPRG0 000000003dbe0308 SPRG1 000000003e669fe0 SPRG2 00000000000000d8 SPRG3 000000003dbe0308
SPRG4 0000000000000000 SPRG5 0000000000000000 SPRG6 0000000000000000 SPRG7 0000000000000000
HSRR0 6d61676963313230 HSRR1 0000000000000000
CFAR 000000003dbe3e64
LPCR 0000000004020008
PTCR 0000000000000000 DAR 0000000000000000 DSISR 0000000000000000
Aborted (core dumped)
To fix this, set the PSSCR_EC bit when a vcpu is stopped to disable it
from coming back online until the start-cpu rtas call is made.
Fixes: 21c0d66a9c
("target/ppc: Fix support for "STOP light" states on POWER9")
Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Message-Id: <20190516005744.24366-1-sjitindarsingh@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
407 lines
11 KiB
C
407 lines
11 KiB
C
/*
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* sPAPR CPU core device, acts as container of CPU thread devices.
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*
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* Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "hw/cpu/core.h"
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#include "hw/ppc/spapr_cpu_core.h"
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#include "target/ppc/cpu.h"
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#include "hw/ppc/spapr.h"
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#include "hw/boards.h"
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#include "qapi/error.h"
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#include "sysemu/cpus.h"
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#include "sysemu/kvm.h"
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#include "target/ppc/kvm_ppc.h"
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#include "hw/ppc/ppc.h"
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#include "target/ppc/mmu-hash64.h"
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#include "sysemu/numa.h"
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#include "sysemu/hw_accel.h"
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#include "qemu/error-report.h"
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static void spapr_cpu_reset(void *opaque)
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{
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PowerPCCPU *cpu = opaque;
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CPUState *cs = CPU(cpu);
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CPUPPCState *env = &cpu->env;
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PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
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SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
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target_ulong lpcr;
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cpu_reset(cs);
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/* All CPUs start halted. CPU0 is unhalted from the machine level
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* reset code and the rest are explicitly started up by the guest
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* using an RTAS call */
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cs->halted = 1;
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/* Set compatibility mode to match the boot CPU, which was either set
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* by the machine reset code or by CAS. This should never fail.
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*/
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ppc_set_compat(cpu, POWERPC_CPU(first_cpu)->compat_pvr, &error_abort);
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env->spr[SPR_HIOR] = 0;
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lpcr = env->spr[SPR_LPCR];
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/* Set emulated LPCR to not send interrupts to hypervisor. Note that
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* under KVM, the actual HW LPCR will be set differently by KVM itself,
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* the settings below ensure proper operations with TCG in absence of
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* a real hypervisor.
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*
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* Clearing VPM0 will also cause us to use RMOR in mmu-hash64.c for
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* real mode accesses, which thankfully defaults to 0 and isn't
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* accessible in guest mode.
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*
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* Disable Power-saving mode Exit Cause exceptions for the CPU, so
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* we don't get spurious wakups before an RTAS start-cpu call.
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* For the same reason, set PSSCR_EC.
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*/
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lpcr &= ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm);
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lpcr |= LPCR_LPES0 | LPCR_LPES1;
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env->spr[SPR_PSSCR] |= PSSCR_EC;
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/* Set RMLS to the max (ie, 16G) */
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lpcr &= ~LPCR_RMLS;
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lpcr |= 1ull << LPCR_RMLS_SHIFT;
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ppc_store_lpcr(cpu, lpcr);
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/* Set a full AMOR so guest can use the AMR as it sees fit */
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env->spr[SPR_AMOR] = 0xffffffffffffffffull;
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spapr_cpu->vpa_addr = 0;
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spapr_cpu->slb_shadow_addr = 0;
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spapr_cpu->slb_shadow_size = 0;
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spapr_cpu->dtl_addr = 0;
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spapr_cpu->dtl_size = 0;
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spapr_caps_cpu_apply(SPAPR_MACHINE(qdev_get_machine()), cpu);
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kvm_check_mmu(cpu, &error_fatal);
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}
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void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_ulong r3)
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{
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PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
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CPUPPCState *env = &cpu->env;
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env->nip = nip;
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env->gpr[3] = r3;
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kvmppc_set_reg_ppc_online(cpu, 1);
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CPU(cpu)->halted = 0;
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/* Enable Power-saving mode Exit Cause exceptions */
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ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm);
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}
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/*
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* Return the sPAPR CPU core type for @model which essentially is the CPU
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* model specified with -cpu cmdline option.
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*/
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const char *spapr_get_cpu_core_type(const char *cpu_type)
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{
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int len = strlen(cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
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char *core_type = g_strdup_printf(SPAPR_CPU_CORE_TYPE_NAME("%.*s"),
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len, cpu_type);
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ObjectClass *oc = object_class_by_name(core_type);
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g_free(core_type);
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if (!oc) {
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return NULL;
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}
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return object_class_get_name(oc);
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}
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static bool slb_shadow_needed(void *opaque)
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{
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SpaprCpuState *spapr_cpu = opaque;
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return spapr_cpu->slb_shadow_addr != 0;
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}
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static const VMStateDescription vmstate_spapr_cpu_slb_shadow = {
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.name = "spapr_cpu/vpa/slb_shadow",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = slb_shadow_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(slb_shadow_addr, SpaprCpuState),
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VMSTATE_UINT64(slb_shadow_size, SpaprCpuState),
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VMSTATE_END_OF_LIST()
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}
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};
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static bool dtl_needed(void *opaque)
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{
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SpaprCpuState *spapr_cpu = opaque;
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return spapr_cpu->dtl_addr != 0;
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}
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static const VMStateDescription vmstate_spapr_cpu_dtl = {
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.name = "spapr_cpu/vpa/dtl",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = dtl_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(dtl_addr, SpaprCpuState),
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VMSTATE_UINT64(dtl_size, SpaprCpuState),
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VMSTATE_END_OF_LIST()
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}
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};
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static bool vpa_needed(void *opaque)
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{
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SpaprCpuState *spapr_cpu = opaque;
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return spapr_cpu->vpa_addr != 0;
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}
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static const VMStateDescription vmstate_spapr_cpu_vpa = {
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.name = "spapr_cpu/vpa",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = vpa_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(vpa_addr, SpaprCpuState),
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VMSTATE_END_OF_LIST()
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},
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.subsections = (const VMStateDescription * []) {
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&vmstate_spapr_cpu_slb_shadow,
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&vmstate_spapr_cpu_dtl,
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NULL
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}
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};
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static const VMStateDescription vmstate_spapr_cpu_state = {
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.name = "spapr_cpu",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_END_OF_LIST()
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},
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.subsections = (const VMStateDescription * []) {
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&vmstate_spapr_cpu_vpa,
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NULL
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}
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};
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static void spapr_unrealize_vcpu(PowerPCCPU *cpu, SpaprCpuCore *sc)
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{
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if (!sc->pre_3_0_migration) {
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vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data);
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}
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qemu_unregister_reset(spapr_cpu_reset, cpu);
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if (spapr_cpu_state(cpu)->icp) {
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object_unparent(OBJECT(spapr_cpu_state(cpu)->icp));
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}
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if (spapr_cpu_state(cpu)->tctx) {
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object_unparent(OBJECT(spapr_cpu_state(cpu)->tctx));
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}
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cpu_remove_sync(CPU(cpu));
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object_unparent(OBJECT(cpu));
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}
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static void spapr_cpu_core_unrealize(DeviceState *dev, Error **errp)
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{
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SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
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CPUCore *cc = CPU_CORE(dev);
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int i;
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for (i = 0; i < cc->nr_threads; i++) {
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spapr_unrealize_vcpu(sc->threads[i], sc);
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}
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g_free(sc->threads);
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}
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static void spapr_realize_vcpu(PowerPCCPU *cpu, SpaprMachineState *spapr,
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SpaprCpuCore *sc, Error **errp)
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{
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CPUPPCState *env = &cpu->env;
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CPUState *cs = CPU(cpu);
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Error *local_err = NULL;
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object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
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if (local_err) {
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goto error;
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}
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/* Set time-base frequency to 512 MHz */
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cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);
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cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr));
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kvmppc_set_papr(cpu);
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qemu_register_reset(spapr_cpu_reset, cpu);
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spapr_cpu_reset(cpu);
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spapr->irq->cpu_intc_create(spapr, cpu, &local_err);
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if (local_err) {
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goto error_unregister;
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}
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if (!sc->pre_3_0_migration) {
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vmstate_register(NULL, cs->cpu_index, &vmstate_spapr_cpu_state,
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cpu->machine_data);
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}
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return;
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error_unregister:
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qemu_unregister_reset(spapr_cpu_reset, cpu);
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cpu_remove_sync(CPU(cpu));
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error:
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error_propagate(errp, local_err);
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}
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static PowerPCCPU *spapr_create_vcpu(SpaprCpuCore *sc, int i, Error **errp)
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{
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SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(sc);
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CPUCore *cc = CPU_CORE(sc);
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Object *obj;
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char *id;
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CPUState *cs;
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PowerPCCPU *cpu;
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Error *local_err = NULL;
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obj = object_new(scc->cpu_type);
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cs = CPU(obj);
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cpu = POWERPC_CPU(obj);
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cs->cpu_index = cc->core_id + i;
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spapr_set_vcpu_id(cpu, cs->cpu_index, &local_err);
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if (local_err) {
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goto err;
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}
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cpu->node_id = sc->node_id;
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id = g_strdup_printf("thread[%d]", i);
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object_property_add_child(OBJECT(sc), id, obj, &local_err);
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g_free(id);
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if (local_err) {
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goto err;
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}
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cpu->machine_data = g_new0(SpaprCpuState, 1);
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object_unref(obj);
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return cpu;
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err:
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object_unref(obj);
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error_propagate(errp, local_err);
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return NULL;
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}
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static void spapr_delete_vcpu(PowerPCCPU *cpu, SpaprCpuCore *sc)
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{
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SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
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cpu->machine_data = NULL;
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g_free(spapr_cpu);
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object_unparent(OBJECT(cpu));
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}
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static void spapr_cpu_core_realize(DeviceState *dev, Error **errp)
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{
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/* We don't use SPAPR_MACHINE() in order to exit gracefully if the user
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* tries to add a sPAPR CPU core to a non-pseries machine.
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*/
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SpaprMachineState *spapr =
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(SpaprMachineState *) object_dynamic_cast(qdev_get_machine(),
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TYPE_SPAPR_MACHINE);
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SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
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CPUCore *cc = CPU_CORE(OBJECT(dev));
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Error *local_err = NULL;
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int i, j;
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if (!spapr) {
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error_setg(errp, TYPE_SPAPR_CPU_CORE " needs a pseries machine");
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return;
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}
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sc->threads = g_new(PowerPCCPU *, cc->nr_threads);
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for (i = 0; i < cc->nr_threads; i++) {
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sc->threads[i] = spapr_create_vcpu(sc, i, &local_err);
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if (local_err) {
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goto err;
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}
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}
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for (j = 0; j < cc->nr_threads; j++) {
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spapr_realize_vcpu(sc->threads[j], spapr, sc, &local_err);
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if (local_err) {
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goto err_unrealize;
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}
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}
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return;
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err_unrealize:
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while (--j >= 0) {
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spapr_unrealize_vcpu(sc->threads[j], sc);
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}
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err:
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while (--i >= 0) {
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spapr_delete_vcpu(sc->threads[i], sc);
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}
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g_free(sc->threads);
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error_propagate(errp, local_err);
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}
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static Property spapr_cpu_core_properties[] = {
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DEFINE_PROP_INT32("node-id", SpaprCpuCore, node_id, CPU_UNSET_NUMA_NODE_ID),
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DEFINE_PROP_BOOL("pre-3.0-migration", SpaprCpuCore, pre_3_0_migration,
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false),
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DEFINE_PROP_END_OF_LIST()
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};
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static void spapr_cpu_core_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc);
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dc->realize = spapr_cpu_core_realize;
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dc->unrealize = spapr_cpu_core_unrealize;
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dc->props = spapr_cpu_core_properties;
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scc->cpu_type = data;
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}
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#define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \
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{ \
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.parent = TYPE_SPAPR_CPU_CORE, \
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.class_data = (void *) POWERPC_CPU_TYPE_NAME(cpu_model), \
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.class_init = spapr_cpu_core_class_init, \
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.name = SPAPR_CPU_CORE_TYPE_NAME(cpu_model), \
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}
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static const TypeInfo spapr_cpu_core_type_infos[] = {
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{
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.name = TYPE_SPAPR_CPU_CORE,
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.parent = TYPE_CPU_CORE,
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.abstract = true,
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.instance_size = sizeof(SpaprCpuCore),
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.class_size = sizeof(SpaprCpuCoreClass),
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},
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DEFINE_SPAPR_CPU_CORE_TYPE("970_v2.2"),
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DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.0"),
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DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.1"),
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DEFINE_SPAPR_CPU_CORE_TYPE("power5+_v2.1"),
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DEFINE_SPAPR_CPU_CORE_TYPE("power7_v2.3"),
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DEFINE_SPAPR_CPU_CORE_TYPE("power7+_v2.1"),
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DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"),
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DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"),
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DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"),
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DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"),
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DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"),
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#ifdef CONFIG_KVM
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DEFINE_SPAPR_CPU_CORE_TYPE("host"),
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#endif
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};
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DEFINE_TYPES(spapr_cpu_core_type_infos)
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