Anup Patel 71a150bc91 target/riscv/pmp.c: Fix pmp_decode_napot() ... Currently, start and end address of a PMP region are not decoded correctly by pmp_decode_napot(). Let's say we have a 128KB PMP region with base address as 0x80000000. Now, the PMPADDRx CSR value for this region will be 0x20003fff. The current pmp_decode_napot() implementation will decode PMPADDRx CSR as t1=14, base=0x100000000, and range=0x1ffff whereas it should have decoded PMPADDRx CSR as t1=14, base=0x80000000, and range=0x1fff. This patch fixes the base value decoding in pmp_decode_napot() when PMPADDRx CSR is not -1 (i.e. 0xffffffffffffffff). Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2018-12-20 12:26:39 -08:00
..
cpu.c	RISC-V: Update CSR and interrupt definitions	2018-10-17 13:02:19 -07:00
cpu.h	RISC-V: Allow setting and clearing multiple irqs	2018-10-17 13:02:09 -07:00
cpu_bits.h	RISC-V: Update CSR and interrupt definitions	2018-10-17 13:02:19 -07:00
cpu_helper.c	RISC-V: Add hartid and \n to interrupt logging	2018-12-20 12:08:42 -08:00
cpu_user.h	RISC-V Linux User Emulation	2018-03-07 08:30:28 +13:00
fpu_helper.c	target/riscv: Remove floatX_maybe_silence_nan from conversions	2018-05-17 15:27:15 -07:00
gdbstub.c	RISC-V GDB Stub	2018-03-07 08:30:28 +13:00
helper.h	RISC-V CPU Helpers	2018-03-07 08:30:28 +13:00
instmap.h	RISC-V TCG Code Generation	2018-03-07 08:30:28 +13:00
Makefile.objs	RISC-V: Move non-ops from op_helper to cpu_helper	2018-10-17 13:02:14 -07:00
op_helper.c	RISC-V: Update CSR and interrupt definitions	2018-10-17 13:02:19 -07:00
pmp.c	target/riscv/pmp.c: Fix pmp_decode_napot()	2018-12-20 12:26:39 -08:00
pmp.h	RISC-V Physical Memory Protection	2018-03-07 08:30:28 +13:00
translate.c	RISC-V: Respect fences for user-only emulators	2018-11-13 15:12:15 -08:00