72b3b8f24a
Don't expect that CCOUNT increments are equal to the number of executed instructions. Verify that timer interrupt does not fire before the programmed CCOMPARE value and does fire after. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
184 lines
3.4 KiB
ArmAsm
184 lines
3.4 KiB
ArmAsm
#include "macros.inc"
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#define CCOUNT_SHIFT 4
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#define WAIT_LOOPS 20
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.macro make_ccount_delta target, delta
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rsr \delta, ccount
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rsr \target, ccount
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sub \delta, \target, \delta
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slli \delta, \delta, CCOUNT_SHIFT
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add \target, \target, \delta
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.endm
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test_suite timer
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test ccount
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rsr a3, ccount
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rsr a4, ccount
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assert ne, a3, a4
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test_end
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test ccompare
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movi a2, 0
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wsr a2, intenable
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rsr a2, interrupt
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wsr a2, intclear
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movi a2, 0
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wsr a2, ccompare1
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wsr a2, ccompare2
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make_ccount_delta a2, a15
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wsr a2, ccompare0
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1:
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rsr a3, interrupt
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rsr a4, ccount
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rsr a5, interrupt
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sub a4, a4, a2
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bgez a4, 2f
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assert eqi, a3, 0
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j 1b
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2:
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assert nei, a5, 0
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test_end
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test ccompare0_interrupt
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set_vector kernel, 2f
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movi a2, 0
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wsr a2, intenable
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rsr a2, interrupt
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wsr a2, intclear
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movi a2, 0
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wsr a2, ccompare1
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wsr a2, ccompare2
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movi a3, WAIT_LOOPS
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make_ccount_delta a2, a15
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wsr a2, ccompare0
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rsync
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rsr a2, interrupt
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assert eqi, a2, 0
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movi a2, 0x40
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wsr a2, intenable
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rsil a2, 0
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loop a3, 1f
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nop
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1:
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test_fail
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2:
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rsr a2, exccause
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assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */
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test_end
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test ccompare1_interrupt
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set_vector level3, 2f
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movi a2, 0
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wsr a2, intenable
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rsr a2, interrupt
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wsr a2, intclear
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movi a2, 0
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wsr a2, ccompare0
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wsr a2, ccompare2
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movi a3, WAIT_LOOPS
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make_ccount_delta a2, a15
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wsr a2, ccompare1
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rsync
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rsr a2, interrupt
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assert eqi, a2, 0
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movi a2, 0x400
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wsr a2, intenable
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rsil a2, 2
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loop a3, 1f
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nop
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1:
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test_fail
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2:
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test_end
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test ccompare2_interrupt
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set_vector level5, 2f
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movi a2, 0
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wsr a2, intenable
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rsr a2, interrupt
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wsr a2, intclear
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movi a2, 0
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wsr a2, ccompare0
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wsr a2, ccompare1
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movi a3, WAIT_LOOPS
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make_ccount_delta a2, a15
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wsr a2, ccompare2
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rsync
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rsr a2, interrupt
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assert eqi, a2, 0
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movi a2, 0x2000
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wsr a2, intenable
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rsil a2, 4
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loop a3, 1f
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nop
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1:
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test_fail
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2:
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test_end
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test ccompare_interrupt_masked
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set_vector kernel, 2f
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movi a2, 0
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wsr a2, intenable
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rsr a2, interrupt
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wsr a2, intclear
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movi a2, 0
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wsr a2, ccompare2
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movi a3, 2 * WAIT_LOOPS
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make_ccount_delta a2, a15
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wsr a2, ccompare1
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add a2, a2, a15
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wsr a2, ccompare0
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rsync
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rsr a2, interrupt
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assert eqi, a2, 0
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movi a2, 0x40
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wsr a2, intenable
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rsil a2, 0
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loop a3, 1f
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nop
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1:
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test_fail
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2:
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rsr a2, exccause
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assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */
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test_end
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test ccompare_interrupt_masked_waiti
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set_vector kernel, 2f
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movi a2, 0
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wsr a2, intenable
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rsr a2, interrupt
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wsr a2, intclear
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movi a2, 0
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wsr a2, ccompare2
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movi a3, 2 * WAIT_LOOPS
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make_ccount_delta a2, a15
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wsr a2, ccompare1
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add a2, a2, a15
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wsr a2, ccompare0
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rsync
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rsr a2, interrupt
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assert eqi, a2, 0
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movi a2, 0x40
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wsr a2, intenable
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waiti 0
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test_fail
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2:
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rsr a2, exccause
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assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */
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test_end
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test_suite_end
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