Use the external qemu-timer API instead. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
691 lines
19 KiB
C
691 lines
19 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* KVM/MIPS: MIPS specific KVM APIs
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*
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* Copyright (C) 2012-2014 Imagination Technologies Ltd.
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* Authors: Sanjay Lal <sanjayl@kymasys.com>
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*/
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#include <sys/types.h>
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#include <sys/ioctl.h>
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#include <sys/mman.h>
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#include <linux/kvm.h>
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#include "qemu-common.h"
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#include "qemu/error-report.h"
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#include "qemu/timer.h"
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#include "sysemu/sysemu.h"
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#include "sysemu/kvm.h"
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#include "cpu.h"
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#include "sysemu/cpus.h"
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#include "kvm_mips.h"
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#define DEBUG_KVM 0
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#define DPRINTF(fmt, ...) \
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do { if (DEBUG_KVM) { fprintf(stderr, fmt, ## __VA_ARGS__); } } while (0)
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const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
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KVM_CAP_LAST_INFO
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};
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static void kvm_mips_update_state(void *opaque, int running, RunState state);
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unsigned long kvm_arch_vcpu_id(CPUState *cs)
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{
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return cs->cpu_index;
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}
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int kvm_arch_init(KVMState *s)
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{
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/* MIPS has 128 signals */
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kvm_set_sigmask_len(s, 16);
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DPRINTF("%s\n", __func__);
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return 0;
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}
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int kvm_arch_init_vcpu(CPUState *cs)
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{
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int ret = 0;
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qemu_add_vm_change_state_handler(kvm_mips_update_state, cs);
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DPRINTF("%s\n", __func__);
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return ret;
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}
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void kvm_mips_reset_vcpu(MIPSCPU *cpu)
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{
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CPUMIPSState *env = &cpu->env;
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if (env->CP0_Config1 & (1 << CP0C1_FP)) {
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fprintf(stderr, "Warning: FPU not supported with KVM, disabling\n");
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env->CP0_Config1 &= ~(1 << CP0C1_FP);
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}
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DPRINTF("%s\n", __func__);
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}
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int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
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{
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DPRINTF("%s\n", __func__);
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return 0;
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}
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int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
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{
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DPRINTF("%s\n", __func__);
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return 0;
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}
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static inline int cpu_mips_io_interrupts_pending(MIPSCPU *cpu)
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{
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CPUMIPSState *env = &cpu->env;
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DPRINTF("%s: %#x\n", __func__, env->CP0_Cause & (1 << (2 + CP0Ca_IP)));
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return env->CP0_Cause & (0x1 << (2 + CP0Ca_IP));
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}
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void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
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{
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MIPSCPU *cpu = MIPS_CPU(cs);
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int r;
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struct kvm_mips_interrupt intr;
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if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
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cpu_mips_io_interrupts_pending(cpu)) {
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intr.cpu = -1;
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intr.irq = 2;
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r = kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr);
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if (r < 0) {
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error_report("%s: cpu %d: failed to inject IRQ %x",
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__func__, cs->cpu_index, intr.irq);
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}
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}
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}
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void kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
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{
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DPRINTF("%s\n", __func__);
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}
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int kvm_arch_process_async_events(CPUState *cs)
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{
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return cs->halted;
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}
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int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
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{
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int ret;
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DPRINTF("%s\n", __func__);
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switch (run->exit_reason) {
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default:
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error_report("%s: unknown exit reason %d",
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__func__, run->exit_reason);
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ret = -1;
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break;
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}
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return ret;
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}
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bool kvm_arch_stop_on_emulation_error(CPUState *cs)
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{
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DPRINTF("%s\n", __func__);
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return true;
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}
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int kvm_arch_on_sigbus_vcpu(CPUState *cs, int code, void *addr)
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{
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DPRINTF("%s\n", __func__);
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return 1;
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}
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int kvm_arch_on_sigbus(int code, void *addr)
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{
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DPRINTF("%s\n", __func__);
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return 1;
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}
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void kvm_arch_init_irq_routing(KVMState *s)
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{
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}
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int kvm_mips_set_interrupt(MIPSCPU *cpu, int irq, int level)
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{
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CPUState *cs = CPU(cpu);
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struct kvm_mips_interrupt intr;
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if (!kvm_enabled()) {
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return 0;
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}
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intr.cpu = -1;
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if (level) {
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intr.irq = irq;
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} else {
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intr.irq = -irq;
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}
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kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr);
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return 0;
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}
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int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level)
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{
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CPUState *cs = current_cpu;
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CPUState *dest_cs = CPU(cpu);
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struct kvm_mips_interrupt intr;
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if (!kvm_enabled()) {
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return 0;
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}
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intr.cpu = dest_cs->cpu_index;
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if (level) {
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intr.irq = irq;
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} else {
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intr.irq = -irq;
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}
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DPRINTF("%s: CPU %d, IRQ: %d\n", __func__, intr.cpu, intr.irq);
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kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr);
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return 0;
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}
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#define MIPS_CP0_32(_R, _S) \
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(KVM_REG_MIPS | KVM_REG_SIZE_U32 | 0x10000 | (8 * (_R) + (_S)))
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#define MIPS_CP0_64(_R, _S) \
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(KVM_REG_MIPS | KVM_REG_SIZE_U64 | 0x10000 | (8 * (_R) + (_S)))
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#define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0)
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#define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0)
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#define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2)
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#define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0)
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#define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0)
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#define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0)
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#define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0)
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#define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0)
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#define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0)
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#define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0)
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#define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0)
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#define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0)
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#define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0)
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#define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0)
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/* CP0_Count control */
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#define KVM_REG_MIPS_COUNT_CTL (KVM_REG_MIPS | KVM_REG_SIZE_U64 | \
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0x20000 | 0)
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#define KVM_REG_MIPS_COUNT_CTL_DC 0x00000001 /* master disable */
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/* CP0_Count resume monotonic nanoseconds */
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#define KVM_REG_MIPS_COUNT_RESUME (KVM_REG_MIPS | KVM_REG_SIZE_U64 | \
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0x20000 | 1)
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/* CP0_Count rate in Hz */
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#define KVM_REG_MIPS_COUNT_HZ (KVM_REG_MIPS | KVM_REG_SIZE_U64 | \
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0x20000 | 2)
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static inline int kvm_mips_put_one_reg(CPUState *cs, uint64_t reg_id,
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int32_t *addr)
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{
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uint64_t val64 = *addr;
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struct kvm_one_reg cp0reg = {
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.id = reg_id,
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.addr = (uintptr_t)&val64
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};
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return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg);
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}
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static inline int kvm_mips_put_one_ulreg(CPUState *cs, uint64_t reg_id,
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target_ulong *addr)
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{
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uint64_t val64 = *addr;
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struct kvm_one_reg cp0reg = {
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.id = reg_id,
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.addr = (uintptr_t)&val64
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};
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return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg);
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}
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static inline int kvm_mips_put_one_reg64(CPUState *cs, uint64_t reg_id,
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uint64_t *addr)
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{
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struct kvm_one_reg cp0reg = {
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.id = reg_id,
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.addr = (uintptr_t)addr
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};
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return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &cp0reg);
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}
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static inline int kvm_mips_get_one_reg(CPUState *cs, uint64_t reg_id,
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int32_t *addr)
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{
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int ret;
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uint64_t val64 = 0;
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struct kvm_one_reg cp0reg = {
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.id = reg_id,
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.addr = (uintptr_t)&val64
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};
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ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg);
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if (ret >= 0) {
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*addr = val64;
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}
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return ret;
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}
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static inline int kvm_mips_get_one_ulreg(CPUState *cs, uint64 reg_id,
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target_ulong *addr)
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{
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int ret;
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uint64_t val64 = 0;
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struct kvm_one_reg cp0reg = {
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.id = reg_id,
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.addr = (uintptr_t)&val64
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};
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ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg);
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if (ret >= 0) {
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*addr = val64;
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}
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return ret;
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}
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static inline int kvm_mips_get_one_reg64(CPUState *cs, uint64 reg_id,
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uint64_t *addr)
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{
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struct kvm_one_reg cp0reg = {
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.id = reg_id,
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.addr = (uintptr_t)addr
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};
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return kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &cp0reg);
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}
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/*
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* We freeze the KVM timer when either the VM clock is stopped or the state is
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* saved (the state is dirty).
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*/
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/*
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* Save the state of the KVM timer when VM clock is stopped or state is synced
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* to QEMU.
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*/
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static int kvm_mips_save_count(CPUState *cs)
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{
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MIPSCPU *cpu = MIPS_CPU(cs);
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CPUMIPSState *env = &cpu->env;
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uint64_t count_ctl;
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int err, ret = 0;
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/* freeze KVM timer */
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err = kvm_mips_get_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
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if (err < 0) {
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DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__, err);
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ret = err;
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} else if (!(count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) {
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count_ctl |= KVM_REG_MIPS_COUNT_CTL_DC;
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err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
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if (err < 0) {
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DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__, err);
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ret = err;
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}
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}
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/* read CP0_Cause */
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err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CAUSE, &env->CP0_Cause);
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if (err < 0) {
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DPRINTF("%s: Failed to get CP0_CAUSE (%d)\n", __func__, err);
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ret = err;
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}
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/* read CP0_Count */
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err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_COUNT, &env->CP0_Count);
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if (err < 0) {
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DPRINTF("%s: Failed to get CP0_COUNT (%d)\n", __func__, err);
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ret = err;
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}
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return ret;
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}
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/*
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* Restore the state of the KVM timer when VM clock is restarted or state is
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* synced to KVM.
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*/
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static int kvm_mips_restore_count(CPUState *cs)
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{
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MIPSCPU *cpu = MIPS_CPU(cs);
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CPUMIPSState *env = &cpu->env;
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uint64_t count_ctl;
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int err_dc, err, ret = 0;
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/* check the timer is frozen */
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err_dc = kvm_mips_get_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
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if (err_dc < 0) {
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DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__, err_dc);
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ret = err_dc;
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} else if (!(count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)) {
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/* freeze timer (sets COUNT_RESUME for us) */
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count_ctl |= KVM_REG_MIPS_COUNT_CTL_DC;
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err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
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if (err < 0) {
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DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__, err);
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ret = err;
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}
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}
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/* load CP0_Cause */
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err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_CAUSE, &env->CP0_Cause);
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if (err < 0) {
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DPRINTF("%s: Failed to put CP0_CAUSE (%d)\n", __func__, err);
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ret = err;
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}
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/* load CP0_Count */
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err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_COUNT, &env->CP0_Count);
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if (err < 0) {
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DPRINTF("%s: Failed to put CP0_COUNT (%d)\n", __func__, err);
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ret = err;
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}
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/* resume KVM timer */
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if (err_dc >= 0) {
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count_ctl &= ~KVM_REG_MIPS_COUNT_CTL_DC;
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err = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_CTL, &count_ctl);
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if (err < 0) {
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DPRINTF("%s: Failed to set COUNT_CTL.DC=0 (%d)\n", __func__, err);
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ret = err;
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}
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}
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return ret;
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}
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/*
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* Handle the VM clock being started or stopped
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*/
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static void kvm_mips_update_state(void *opaque, int running, RunState state)
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{
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CPUState *cs = opaque;
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int ret;
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uint64_t count_resume;
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/*
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* If state is already dirty (synced to QEMU) then the KVM timer state is
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* already saved and can be restored when it is synced back to KVM.
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*/
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if (!running) {
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if (!cs->kvm_vcpu_dirty) {
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ret = kvm_mips_save_count(cs);
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if (ret < 0) {
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fprintf(stderr, "Failed saving count\n");
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}
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}
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} else {
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/* Set clock restore time to now */
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count_resume = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
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ret = kvm_mips_put_one_reg64(cs, KVM_REG_MIPS_COUNT_RESUME,
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&count_resume);
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if (ret < 0) {
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fprintf(stderr, "Failed setting COUNT_RESUME\n");
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return;
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}
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if (!cs->kvm_vcpu_dirty) {
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ret = kvm_mips_restore_count(cs);
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if (ret < 0) {
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fprintf(stderr, "Failed restoring count\n");
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}
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}
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}
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}
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static int kvm_mips_put_cp0_registers(CPUState *cs, int level)
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{
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MIPSCPU *cpu = MIPS_CPU(cs);
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CPUMIPSState *env = &cpu->env;
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int err, ret = 0;
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(void)level;
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err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index);
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if (err < 0) {
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DPRINTF("%s: Failed to put CP0_INDEX (%d)\n", __func__, err);
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ret = err;
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}
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err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT,
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&env->CP0_Context);
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if (err < 0) {
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DPRINTF("%s: Failed to put CP0_CONTEXT (%d)\n", __func__, err);
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ret = err;
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}
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err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_USERLOCAL,
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&env->active_tc.CP0_UserLocal);
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if (err < 0) {
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DPRINTF("%s: Failed to put CP0_USERLOCAL (%d)\n", __func__, err);
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ret = err;
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}
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err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PAGEMASK,
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&env->CP0_PageMask);
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if (err < 0) {
|
|
DPRINTF("%s: Failed to put CP0_PAGEMASK (%d)\n", __func__, err);
|
|
ret = err;
|
|
}
|
|
err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired);
|
|
if (err < 0) {
|
|
DPRINTF("%s: Failed to put CP0_WIRED (%d)\n", __func__, err);
|
|
ret = err;
|
|
}
|
|
err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna);
|
|
if (err < 0) {
|
|
DPRINTF("%s: Failed to put CP0_HWRENA (%d)\n", __func__, err);
|
|
ret = err;
|
|
}
|
|
err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_BADVADDR,
|
|
&env->CP0_BadVAddr);
|
|
if (err < 0) {
|
|
DPRINTF("%s: Failed to put CP0_BADVADDR (%d)\n", __func__, err);
|
|
ret = err;
|
|
}
|
|
|
|
/* If VM clock stopped then state will be restored when it is restarted */
|
|
if (runstate_is_running()) {
|
|
err = kvm_mips_restore_count(cs);
|
|
if (err < 0) {
|
|
ret = err;
|
|
}
|
|
}
|
|
|
|
err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ENTRYHI,
|
|
&env->CP0_EntryHi);
|
|
if (err < 0) {
|
|
DPRINTF("%s: Failed to put CP0_ENTRYHI (%d)\n", __func__, err);
|
|
ret = err;
|
|
}
|
|
err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_COMPARE,
|
|
&env->CP0_Compare);
|
|
if (err < 0) {
|
|
DPRINTF("%s: Failed to put CP0_COMPARE (%d)\n", __func__, err);
|
|
ret = err;
|
|
}
|
|
err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_STATUS, &env->CP0_Status);
|
|
if (err < 0) {
|
|
DPRINTF("%s: Failed to put CP0_STATUS (%d)\n", __func__, err);
|
|
ret = err;
|
|
}
|
|
err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_EPC, &env->CP0_EPC);
|
|
if (err < 0) {
|
|
DPRINTF("%s: Failed to put CP0_EPC (%d)\n", __func__, err);
|
|
ret = err;
|
|
}
|
|
err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC,
|
|
&env->CP0_ErrorEPC);
|
|
if (err < 0) {
|
|
DPRINTF("%s: Failed to put CP0_ERROREPC (%d)\n", __func__, err);
|
|
ret = err;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int kvm_mips_get_cp0_registers(CPUState *cs)
|
|
{
|
|
MIPSCPU *cpu = MIPS_CPU(cs);
|
|
CPUMIPSState *env = &cpu->env;
|
|
int err, ret = 0;
|
|
|
|
err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_INDEX, &env->CP0_Index);
|
|
if (err < 0) {
|
|
DPRINTF("%s: Failed to get CP0_INDEX (%d)\n", __func__, err);
|
|
ret = err;
|
|
}
|
|
err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT,
|
|
&env->CP0_Context);
|
|
if (err < 0) {
|
|
DPRINTF("%s: Failed to get CP0_CONTEXT (%d)\n", __func__, err);
|
|
ret = err;
|
|
}
|
|
err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_USERLOCAL,
|
|
&env->active_tc.CP0_UserLocal);
|
|
if (err < 0) {
|
|
DPRINTF("%s: Failed to get CP0_USERLOCAL (%d)\n", __func__, err);
|
|
ret = err;
|
|
}
|
|
err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PAGEMASK,
|
|
&env->CP0_PageMask);
|
|
if (err < 0) {
|
|
DPRINTF("%s: Failed to get CP0_PAGEMASK (%d)\n", __func__, err);
|
|
ret = err;
|
|
}
|
|
err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired);
|
|
if (err < 0) {
|
|
DPRINTF("%s: Failed to get CP0_WIRED (%d)\n", __func__, err);
|
|
ret = err;
|
|
}
|
|
err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna);
|
|
if (err < 0) {
|
|
DPRINTF("%s: Failed to get CP0_HWRENA (%d)\n", __func__, err);
|
|
ret = err;
|
|
}
|
|
err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_BADVADDR,
|
|
&env->CP0_BadVAddr);
|
|
if (err < 0) {
|
|
DPRINTF("%s: Failed to get CP0_BADVADDR (%d)\n", __func__, err);
|
|
ret = err;
|
|
}
|
|
err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ENTRYHI,
|
|
&env->CP0_EntryHi);
|
|
if (err < 0) {
|
|
DPRINTF("%s: Failed to get CP0_ENTRYHI (%d)\n", __func__, err);
|
|
ret = err;
|
|
}
|
|
err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_COMPARE,
|
|
&env->CP0_Compare);
|
|
if (err < 0) {
|
|
DPRINTF("%s: Failed to get CP0_COMPARE (%d)\n", __func__, err);
|
|
ret = err;
|
|
}
|
|
err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_STATUS, &env->CP0_Status);
|
|
if (err < 0) {
|
|
DPRINTF("%s: Failed to get CP0_STATUS (%d)\n", __func__, err);
|
|
ret = err;
|
|
}
|
|
|
|
/* If VM clock stopped then state was already saved when it was stopped */
|
|
if (runstate_is_running()) {
|
|
err = kvm_mips_save_count(cs);
|
|
if (err < 0) {
|
|
ret = err;
|
|
}
|
|
}
|
|
|
|
err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_EPC, &env->CP0_EPC);
|
|
if (err < 0) {
|
|
DPRINTF("%s: Failed to get CP0_EPC (%d)\n", __func__, err);
|
|
ret = err;
|
|
}
|
|
err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC,
|
|
&env->CP0_ErrorEPC);
|
|
if (err < 0) {
|
|
DPRINTF("%s: Failed to get CP0_ERROREPC (%d)\n", __func__, err);
|
|
ret = err;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
int kvm_arch_put_registers(CPUState *cs, int level)
|
|
{
|
|
MIPSCPU *cpu = MIPS_CPU(cs);
|
|
CPUMIPSState *env = &cpu->env;
|
|
struct kvm_regs regs;
|
|
int ret;
|
|
int i;
|
|
|
|
/* Set the registers based on QEMU's view of things */
|
|
for (i = 0; i < 32; i++) {
|
|
regs.gpr[i] = env->active_tc.gpr[i];
|
|
}
|
|
|
|
regs.hi = env->active_tc.HI[0];
|
|
regs.lo = env->active_tc.LO[0];
|
|
regs.pc = env->active_tc.PC;
|
|
|
|
ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, ®s);
|
|
|
|
if (ret < 0) {
|
|
return ret;
|
|
}
|
|
|
|
ret = kvm_mips_put_cp0_registers(cs, level);
|
|
if (ret < 0) {
|
|
return ret;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
int kvm_arch_get_registers(CPUState *cs)
|
|
{
|
|
MIPSCPU *cpu = MIPS_CPU(cs);
|
|
CPUMIPSState *env = &cpu->env;
|
|
int ret = 0;
|
|
struct kvm_regs regs;
|
|
int i;
|
|
|
|
/* Get the current register set as KVM seems it */
|
|
ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s);
|
|
|
|
if (ret < 0) {
|
|
return ret;
|
|
}
|
|
|
|
for (i = 0; i < 32; i++) {
|
|
env->active_tc.gpr[i] = regs.gpr[i];
|
|
}
|
|
|
|
env->active_tc.HI[0] = regs.hi;
|
|
env->active_tc.LO[0] = regs.lo;
|
|
env->active_tc.PC = regs.pc;
|
|
|
|
kvm_mips_get_cp0_registers(cs);
|
|
|
|
return ret;
|
|
}
|