As part of plumbing MemTxAttrs down to the IOMMU translate method, add MemTxAttrs as an argument to address_space_translate() and address_space_translate_cached(). Callers either have an attrs value to hand, or don't care and can use MEMTXATTRS_UNSPECIFIED. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180521140402.23318-4-peter.maydell@linaro.org
707 lines
18 KiB
C
707 lines
18 KiB
C
/*
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* ARM implementation of KVM hooks
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*
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* Copyright Christoffer Dall 2009-2010
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#include "qemu/osdep.h"
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#include <sys/ioctl.h>
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#include <linux/kvm.h>
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#include "qemu-common.h"
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#include "qemu/timer.h"
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#include "qemu/error-report.h"
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#include "sysemu/sysemu.h"
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#include "sysemu/kvm.h"
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#include "kvm_arm.h"
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#include "cpu.h"
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#include "trace.h"
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#include "internals.h"
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#include "hw/arm/arm.h"
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#include "hw/pci/pci.h"
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#include "exec/memattrs.h"
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#include "exec/address-spaces.h"
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#include "hw/boards.h"
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#include "qemu/log.h"
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const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
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KVM_CAP_LAST_INFO
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};
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static bool cap_has_mp_state;
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static ARMHostCPUFeatures arm_host_cpu_features;
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int kvm_arm_vcpu_init(CPUState *cs)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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struct kvm_vcpu_init init;
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init.target = cpu->kvm_target;
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memcpy(init.features, cpu->kvm_init_features, sizeof(init.features));
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return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init);
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}
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bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try,
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int *fdarray,
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struct kvm_vcpu_init *init)
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{
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int ret, kvmfd = -1, vmfd = -1, cpufd = -1;
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kvmfd = qemu_open("/dev/kvm", O_RDWR);
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if (kvmfd < 0) {
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goto err;
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}
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vmfd = ioctl(kvmfd, KVM_CREATE_VM, 0);
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if (vmfd < 0) {
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goto err;
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}
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cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0);
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if (cpufd < 0) {
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goto err;
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}
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if (!init) {
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/* Caller doesn't want the VCPU to be initialized, so skip it */
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goto finish;
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}
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ret = ioctl(vmfd, KVM_ARM_PREFERRED_TARGET, init);
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if (ret >= 0) {
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ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, init);
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if (ret < 0) {
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goto err;
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}
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} else if (cpus_to_try) {
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/* Old kernel which doesn't know about the
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* PREFERRED_TARGET ioctl: we know it will only support
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* creating one kind of guest CPU which is its preferred
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* CPU type.
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*/
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while (*cpus_to_try != QEMU_KVM_ARM_TARGET_NONE) {
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init->target = *cpus_to_try++;
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memset(init->features, 0, sizeof(init->features));
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ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, init);
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if (ret >= 0) {
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break;
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}
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}
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if (ret < 0) {
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goto err;
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}
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} else {
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/* Treat a NULL cpus_to_try argument the same as an empty
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* list, which means we will fail the call since this must
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* be an old kernel which doesn't support PREFERRED_TARGET.
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*/
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goto err;
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}
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finish:
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fdarray[0] = kvmfd;
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fdarray[1] = vmfd;
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fdarray[2] = cpufd;
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return true;
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err:
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if (cpufd >= 0) {
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close(cpufd);
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}
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if (vmfd >= 0) {
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close(vmfd);
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}
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if (kvmfd >= 0) {
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close(kvmfd);
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}
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return false;
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}
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void kvm_arm_destroy_scratch_host_vcpu(int *fdarray)
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{
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int i;
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for (i = 2; i >= 0; i--) {
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close(fdarray[i]);
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}
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}
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void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
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{
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CPUARMState *env = &cpu->env;
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if (!arm_host_cpu_features.dtb_compatible) {
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if (!kvm_enabled() ||
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!kvm_arm_get_host_cpu_features(&arm_host_cpu_features)) {
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/* We can't report this error yet, so flag that we need to
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* in arm_cpu_realizefn().
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*/
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cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
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cpu->host_cpu_probe_failed = true;
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return;
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}
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}
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cpu->kvm_target = arm_host_cpu_features.target;
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cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible;
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env->features = arm_host_cpu_features.features;
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}
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int kvm_arch_init(MachineState *ms, KVMState *s)
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{
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/* For ARM interrupt delivery is always asynchronous,
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* whether we are using an in-kernel VGIC or not.
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*/
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kvm_async_interrupts_allowed = true;
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/*
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* PSCI wakes up secondary cores, so we always need to
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* have vCPUs waiting in kernel space
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*/
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kvm_halt_in_kernel_allowed = true;
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cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE);
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return 0;
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}
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unsigned long kvm_arch_vcpu_id(CPUState *cpu)
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{
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return cpu->cpu_index;
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}
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/* We track all the KVM devices which need their memory addresses
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* passing to the kernel in a list of these structures.
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* When board init is complete we run through the list and
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* tell the kernel the base addresses of the memory regions.
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* We use a MemoryListener to track mapping and unmapping of
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* the regions during board creation, so the board models don't
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* need to do anything special for the KVM case.
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*/
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typedef struct KVMDevice {
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struct kvm_arm_device_addr kda;
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struct kvm_device_attr kdattr;
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MemoryRegion *mr;
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QSLIST_ENTRY(KVMDevice) entries;
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int dev_fd;
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} KVMDevice;
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static QSLIST_HEAD(kvm_devices_head, KVMDevice) kvm_devices_head;
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static void kvm_arm_devlistener_add(MemoryListener *listener,
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MemoryRegionSection *section)
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{
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KVMDevice *kd;
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QSLIST_FOREACH(kd, &kvm_devices_head, entries) {
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if (section->mr == kd->mr) {
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kd->kda.addr = section->offset_within_address_space;
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}
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}
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}
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static void kvm_arm_devlistener_del(MemoryListener *listener,
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MemoryRegionSection *section)
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{
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KVMDevice *kd;
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QSLIST_FOREACH(kd, &kvm_devices_head, entries) {
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if (section->mr == kd->mr) {
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kd->kda.addr = -1;
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}
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}
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}
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static MemoryListener devlistener = {
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.region_add = kvm_arm_devlistener_add,
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.region_del = kvm_arm_devlistener_del,
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};
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static void kvm_arm_set_device_addr(KVMDevice *kd)
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{
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struct kvm_device_attr *attr = &kd->kdattr;
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int ret;
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/* If the device control API is available and we have a device fd on the
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* KVMDevice struct, let's use the newer API
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*/
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if (kd->dev_fd >= 0) {
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uint64_t addr = kd->kda.addr;
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attr->addr = (uintptr_t)&addr;
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ret = kvm_device_ioctl(kd->dev_fd, KVM_SET_DEVICE_ATTR, attr);
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} else {
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ret = kvm_vm_ioctl(kvm_state, KVM_ARM_SET_DEVICE_ADDR, &kd->kda);
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}
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if (ret < 0) {
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fprintf(stderr, "Failed to set device address: %s\n",
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strerror(-ret));
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abort();
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}
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}
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static void kvm_arm_machine_init_done(Notifier *notifier, void *data)
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{
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KVMDevice *kd, *tkd;
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QSLIST_FOREACH_SAFE(kd, &kvm_devices_head, entries, tkd) {
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if (kd->kda.addr != -1) {
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kvm_arm_set_device_addr(kd);
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}
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memory_region_unref(kd->mr);
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g_free(kd);
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}
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memory_listener_unregister(&devlistener);
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}
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static Notifier notify = {
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.notify = kvm_arm_machine_init_done,
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};
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void kvm_arm_register_device(MemoryRegion *mr, uint64_t devid, uint64_t group,
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uint64_t attr, int dev_fd)
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{
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KVMDevice *kd;
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if (!kvm_irqchip_in_kernel()) {
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return;
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}
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if (QSLIST_EMPTY(&kvm_devices_head)) {
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memory_listener_register(&devlistener, &address_space_memory);
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qemu_add_machine_init_done_notifier(¬ify);
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}
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kd = g_new0(KVMDevice, 1);
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kd->mr = mr;
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kd->kda.id = devid;
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kd->kda.addr = -1;
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kd->kdattr.flags = 0;
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kd->kdattr.group = group;
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kd->kdattr.attr = attr;
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kd->dev_fd = dev_fd;
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QSLIST_INSERT_HEAD(&kvm_devices_head, kd, entries);
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memory_region_ref(kd->mr);
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}
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static int compare_u64(const void *a, const void *b)
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{
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if (*(uint64_t *)a > *(uint64_t *)b) {
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return 1;
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}
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if (*(uint64_t *)a < *(uint64_t *)b) {
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return -1;
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}
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return 0;
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}
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/* Initialize the CPUState's cpreg list according to the kernel's
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* definition of what CPU registers it knows about (and throw away
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* the previous TCG-created cpreg list).
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*/
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int kvm_arm_init_cpreg_list(ARMCPU *cpu)
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{
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struct kvm_reg_list rl;
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struct kvm_reg_list *rlp;
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int i, ret, arraylen;
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CPUState *cs = CPU(cpu);
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rl.n = 0;
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ret = kvm_vcpu_ioctl(cs, KVM_GET_REG_LIST, &rl);
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if (ret != -E2BIG) {
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return ret;
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}
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rlp = g_malloc(sizeof(struct kvm_reg_list) + rl.n * sizeof(uint64_t));
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rlp->n = rl.n;
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ret = kvm_vcpu_ioctl(cs, KVM_GET_REG_LIST, rlp);
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if (ret) {
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goto out;
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}
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/* Sort the list we get back from the kernel, since cpreg_tuples
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* must be in strictly ascending order.
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*/
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qsort(&rlp->reg, rlp->n, sizeof(rlp->reg[0]), compare_u64);
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for (i = 0, arraylen = 0; i < rlp->n; i++) {
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if (!kvm_arm_reg_syncs_via_cpreg_list(rlp->reg[i])) {
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continue;
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}
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switch (rlp->reg[i] & KVM_REG_SIZE_MASK) {
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case KVM_REG_SIZE_U32:
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case KVM_REG_SIZE_U64:
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break;
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default:
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fprintf(stderr, "Can't handle size of register in kernel list\n");
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ret = -EINVAL;
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goto out;
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}
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arraylen++;
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}
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cpu->cpreg_indexes = g_renew(uint64_t, cpu->cpreg_indexes, arraylen);
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cpu->cpreg_values = g_renew(uint64_t, cpu->cpreg_values, arraylen);
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cpu->cpreg_vmstate_indexes = g_renew(uint64_t, cpu->cpreg_vmstate_indexes,
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arraylen);
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cpu->cpreg_vmstate_values = g_renew(uint64_t, cpu->cpreg_vmstate_values,
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arraylen);
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cpu->cpreg_array_len = arraylen;
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cpu->cpreg_vmstate_array_len = arraylen;
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for (i = 0, arraylen = 0; i < rlp->n; i++) {
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uint64_t regidx = rlp->reg[i];
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if (!kvm_arm_reg_syncs_via_cpreg_list(regidx)) {
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continue;
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}
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cpu->cpreg_indexes[arraylen] = regidx;
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arraylen++;
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}
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assert(cpu->cpreg_array_len == arraylen);
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if (!write_kvmstate_to_list(cpu)) {
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/* Shouldn't happen unless kernel is inconsistent about
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* what registers exist.
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*/
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fprintf(stderr, "Initial read of kernel register state failed\n");
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ret = -EINVAL;
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goto out;
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}
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out:
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g_free(rlp);
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return ret;
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}
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bool write_kvmstate_to_list(ARMCPU *cpu)
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{
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CPUState *cs = CPU(cpu);
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int i;
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bool ok = true;
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for (i = 0; i < cpu->cpreg_array_len; i++) {
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struct kvm_one_reg r;
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uint64_t regidx = cpu->cpreg_indexes[i];
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uint32_t v32;
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int ret;
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r.id = regidx;
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switch (regidx & KVM_REG_SIZE_MASK) {
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case KVM_REG_SIZE_U32:
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r.addr = (uintptr_t)&v32;
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ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
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if (!ret) {
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cpu->cpreg_values[i] = v32;
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}
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break;
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case KVM_REG_SIZE_U64:
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r.addr = (uintptr_t)(cpu->cpreg_values + i);
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ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
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break;
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default:
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abort();
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}
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if (ret) {
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ok = false;
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}
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}
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return ok;
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}
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bool write_list_to_kvmstate(ARMCPU *cpu, int level)
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{
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CPUState *cs = CPU(cpu);
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int i;
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bool ok = true;
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for (i = 0; i < cpu->cpreg_array_len; i++) {
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struct kvm_one_reg r;
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uint64_t regidx = cpu->cpreg_indexes[i];
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uint32_t v32;
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int ret;
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if (kvm_arm_cpreg_level(regidx) > level) {
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continue;
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}
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r.id = regidx;
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switch (regidx & KVM_REG_SIZE_MASK) {
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case KVM_REG_SIZE_U32:
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v32 = cpu->cpreg_values[i];
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r.addr = (uintptr_t)&v32;
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break;
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case KVM_REG_SIZE_U64:
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r.addr = (uintptr_t)(cpu->cpreg_values + i);
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break;
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default:
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abort();
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}
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ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
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if (ret) {
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/* We might fail for "unknown register" and also for
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* "you tried to set a register which is constant with
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* a different value from what it actually contains".
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*/
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ok = false;
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}
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}
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return ok;
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}
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void kvm_arm_reset_vcpu(ARMCPU *cpu)
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{
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int ret;
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/* Re-init VCPU so that all registers are set to
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* their respective reset values.
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*/
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ret = kvm_arm_vcpu_init(CPU(cpu));
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if (ret < 0) {
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fprintf(stderr, "kvm_arm_vcpu_init failed: %s\n", strerror(-ret));
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abort();
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}
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if (!write_kvmstate_to_list(cpu)) {
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fprintf(stderr, "write_kvmstate_to_list failed\n");
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abort();
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}
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}
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/*
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* Update KVM's MP_STATE based on what QEMU thinks it is
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*/
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int kvm_arm_sync_mpstate_to_kvm(ARMCPU *cpu)
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{
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if (cap_has_mp_state) {
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struct kvm_mp_state mp_state = {
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.mp_state = (cpu->power_state == PSCI_OFF) ?
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KVM_MP_STATE_STOPPED : KVM_MP_STATE_RUNNABLE
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};
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int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
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if (ret) {
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fprintf(stderr, "%s: failed to set MP_STATE %d/%s\n",
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__func__, ret, strerror(-ret));
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return -1;
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}
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}
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return 0;
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}
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/*
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* Sync the KVM MP_STATE into QEMU
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*/
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int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu)
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{
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if (cap_has_mp_state) {
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struct kvm_mp_state mp_state;
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int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MP_STATE, &mp_state);
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if (ret) {
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fprintf(stderr, "%s: failed to get MP_STATE %d/%s\n",
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__func__, ret, strerror(-ret));
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abort();
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}
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cpu->power_state = (mp_state.mp_state == KVM_MP_STATE_STOPPED) ?
|
|
PSCI_OFF : PSCI_ON;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
|
|
{
|
|
}
|
|
|
|
MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
|
|
{
|
|
ARMCPU *cpu;
|
|
uint32_t switched_level;
|
|
|
|
if (kvm_irqchip_in_kernel()) {
|
|
/*
|
|
* We only need to sync timer states with user-space interrupt
|
|
* controllers, so return early and save cycles if we don't.
|
|
*/
|
|
return MEMTXATTRS_UNSPECIFIED;
|
|
}
|
|
|
|
cpu = ARM_CPU(cs);
|
|
|
|
/* Synchronize our shadowed in-kernel device irq lines with the kvm ones */
|
|
if (run->s.regs.device_irq_level != cpu->device_irq_level) {
|
|
switched_level = cpu->device_irq_level ^ run->s.regs.device_irq_level;
|
|
|
|
qemu_mutex_lock_iothread();
|
|
|
|
if (switched_level & KVM_ARM_DEV_EL1_VTIMER) {
|
|
qemu_set_irq(cpu->gt_timer_outputs[GTIMER_VIRT],
|
|
!!(run->s.regs.device_irq_level &
|
|
KVM_ARM_DEV_EL1_VTIMER));
|
|
switched_level &= ~KVM_ARM_DEV_EL1_VTIMER;
|
|
}
|
|
|
|
if (switched_level & KVM_ARM_DEV_EL1_PTIMER) {
|
|
qemu_set_irq(cpu->gt_timer_outputs[GTIMER_PHYS],
|
|
!!(run->s.regs.device_irq_level &
|
|
KVM_ARM_DEV_EL1_PTIMER));
|
|
switched_level &= ~KVM_ARM_DEV_EL1_PTIMER;
|
|
}
|
|
|
|
if (switched_level & KVM_ARM_DEV_PMU) {
|
|
qemu_set_irq(cpu->pmu_interrupt,
|
|
!!(run->s.regs.device_irq_level & KVM_ARM_DEV_PMU));
|
|
switched_level &= ~KVM_ARM_DEV_PMU;
|
|
}
|
|
|
|
if (switched_level) {
|
|
qemu_log_mask(LOG_UNIMP, "%s: unhandled in-kernel device IRQ %x\n",
|
|
__func__, switched_level);
|
|
}
|
|
|
|
/* We also mark unknown levels as processed to not waste cycles */
|
|
cpu->device_irq_level = run->s.regs.device_irq_level;
|
|
qemu_mutex_unlock_iothread();
|
|
}
|
|
|
|
return MEMTXATTRS_UNSPECIFIED;
|
|
}
|
|
|
|
|
|
int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
|
|
{
|
|
int ret = 0;
|
|
|
|
switch (run->exit_reason) {
|
|
case KVM_EXIT_DEBUG:
|
|
if (kvm_arm_handle_debug(cs, &run->debug.arch)) {
|
|
ret = EXCP_DEBUG;
|
|
} /* otherwise return to guest */
|
|
break;
|
|
default:
|
|
qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
|
|
__func__, run->exit_reason);
|
|
break;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
bool kvm_arch_stop_on_emulation_error(CPUState *cs)
|
|
{
|
|
return true;
|
|
}
|
|
|
|
int kvm_arch_process_async_events(CPUState *cs)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
/* The #ifdef protections are until 32bit headers are imported and can
|
|
* be removed once both 32 and 64 bit reach feature parity.
|
|
*/
|
|
void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg)
|
|
{
|
|
#ifdef KVM_GUESTDBG_USE_SW_BP
|
|
if (kvm_sw_breakpoints_active(cs)) {
|
|
dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
|
|
}
|
|
#endif
|
|
#ifdef KVM_GUESTDBG_USE_HW
|
|
if (kvm_arm_hw_debug_active(cs)) {
|
|
dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW;
|
|
kvm_arm_copy_hw_debug_data(&dbg->arch);
|
|
}
|
|
#endif
|
|
}
|
|
|
|
void kvm_arch_init_irq_routing(KVMState *s)
|
|
{
|
|
}
|
|
|
|
int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
|
|
{
|
|
if (machine_kernel_irqchip_split(ms)) {
|
|
perror("-machine kernel_irqchip=split is not supported on ARM.");
|
|
exit(1);
|
|
}
|
|
|
|
/* If we can create the VGIC using the newer device control API, we
|
|
* let the device do this when it initializes itself, otherwise we
|
|
* fall back to the old API */
|
|
return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL);
|
|
}
|
|
|
|
int kvm_arm_vgic_probe(void)
|
|
{
|
|
if (kvm_create_device(kvm_state,
|
|
KVM_DEV_TYPE_ARM_VGIC_V3, true) == 0) {
|
|
return 3;
|
|
} else if (kvm_create_device(kvm_state,
|
|
KVM_DEV_TYPE_ARM_VGIC_V2, true) == 0) {
|
|
return 2;
|
|
} else {
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
|
|
uint64_t address, uint32_t data, PCIDevice *dev)
|
|
{
|
|
AddressSpace *as = pci_device_iommu_address_space(dev);
|
|
hwaddr xlat, len, doorbell_gpa;
|
|
MemoryRegionSection mrs;
|
|
MemoryRegion *mr;
|
|
int ret = 1;
|
|
|
|
if (as == &address_space_memory) {
|
|
return 0;
|
|
}
|
|
|
|
/* MSI doorbell address is translated by an IOMMU */
|
|
|
|
rcu_read_lock();
|
|
mr = address_space_translate(as, address, &xlat, &len, true,
|
|
MEMTXATTRS_UNSPECIFIED);
|
|
if (!mr) {
|
|
goto unlock;
|
|
}
|
|
mrs = memory_region_find(mr, xlat, 1);
|
|
if (!mrs.mr) {
|
|
goto unlock;
|
|
}
|
|
|
|
doorbell_gpa = mrs.offset_within_address_space;
|
|
memory_region_unref(mrs.mr);
|
|
|
|
route->u.msi.address_lo = doorbell_gpa;
|
|
route->u.msi.address_hi = doorbell_gpa >> 32;
|
|
|
|
trace_kvm_arm_fixup_msi_route(address, doorbell_gpa);
|
|
|
|
ret = 0;
|
|
|
|
unlock:
|
|
rcu_read_unlock();
|
|
return ret;
|
|
}
|
|
|
|
int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
|
|
int vector, PCIDevice *dev)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
int kvm_arch_release_virq_post(int virq)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
int kvm_arch_msi_data_to_gsi(uint32_t data)
|
|
{
|
|
return (data - 32) & 0xffff;
|
|
}
|