Code change produced with: $ git grep '#include "exec/exec-all.h"' | \ cut -d: -f-1 | \ xargs egrep -L "(cpu_address_space_init|cpu_loop_|tlb_|tb_|GETPC|singlestep|TranslationBlock)" | \ xargs sed -i.bak '/#include "exec\/exec-all.h"/d' Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180528232719.4721-10-f4bug@amsat.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
429 lines
13 KiB
C
429 lines
13 KiB
C
/*
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* ARM AdvSIMD / SVE Vector Operations
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*
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* Copyright (c) 2018 Linaro
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/helper-proto.h"
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#include "tcg/tcg-gvec-desc.h"
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#include "fpu/softfloat.h"
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/* Note that vector data is stored in host-endian 64-bit chunks,
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so addressing units smaller than that needs a host-endian fixup. */
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#ifdef HOST_WORDS_BIGENDIAN
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#define H1(x) ((x) ^ 7)
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#define H2(x) ((x) ^ 3)
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#define H4(x) ((x) ^ 1)
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#else
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#define H1(x) (x)
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#define H2(x) (x)
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#define H4(x) (x)
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#endif
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#define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |= CPSR_Q
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static void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz)
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{
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uint64_t *d = vd + opr_sz;
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uintptr_t i;
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for (i = opr_sz; i < max_sz; i += 8) {
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*d++ = 0;
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}
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}
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/* Signed saturating rounding doubling multiply-accumulate high half, 16-bit */
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static uint16_t inl_qrdmlah_s16(CPUARMState *env, int16_t src1,
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int16_t src2, int16_t src3)
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{
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/* Simplify:
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* = ((a3 << 16) + ((e1 * e2) << 1) + (1 << 15)) >> 16
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* = ((a3 << 15) + (e1 * e2) + (1 << 14)) >> 15
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*/
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int32_t ret = (int32_t)src1 * src2;
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ret = ((int32_t)src3 << 15) + ret + (1 << 14);
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ret >>= 15;
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if (ret != (int16_t)ret) {
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SET_QC();
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ret = (ret < 0 ? -0x8000 : 0x7fff);
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}
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return ret;
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}
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uint32_t HELPER(neon_qrdmlah_s16)(CPUARMState *env, uint32_t src1,
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uint32_t src2, uint32_t src3)
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{
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uint16_t e1 = inl_qrdmlah_s16(env, src1, src2, src3);
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uint16_t e2 = inl_qrdmlah_s16(env, src1 >> 16, src2 >> 16, src3 >> 16);
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return deposit32(e1, 16, 16, e2);
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}
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void HELPER(gvec_qrdmlah_s16)(void *vd, void *vn, void *vm,
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void *ve, uint32_t desc)
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{
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uintptr_t opr_sz = simd_oprsz(desc);
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int16_t *d = vd;
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int16_t *n = vn;
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int16_t *m = vm;
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CPUARMState *env = ve;
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uintptr_t i;
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for (i = 0; i < opr_sz / 2; ++i) {
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d[i] = inl_qrdmlah_s16(env, n[i], m[i], d[i]);
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}
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clear_tail(d, opr_sz, simd_maxsz(desc));
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}
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/* Signed saturating rounding doubling multiply-subtract high half, 16-bit */
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static uint16_t inl_qrdmlsh_s16(CPUARMState *env, int16_t src1,
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int16_t src2, int16_t src3)
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{
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/* Similarly, using subtraction:
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* = ((a3 << 16) - ((e1 * e2) << 1) + (1 << 15)) >> 16
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* = ((a3 << 15) - (e1 * e2) + (1 << 14)) >> 15
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*/
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int32_t ret = (int32_t)src1 * src2;
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ret = ((int32_t)src3 << 15) - ret + (1 << 14);
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ret >>= 15;
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if (ret != (int16_t)ret) {
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SET_QC();
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ret = (ret < 0 ? -0x8000 : 0x7fff);
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}
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return ret;
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}
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uint32_t HELPER(neon_qrdmlsh_s16)(CPUARMState *env, uint32_t src1,
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uint32_t src2, uint32_t src3)
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{
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uint16_t e1 = inl_qrdmlsh_s16(env, src1, src2, src3);
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uint16_t e2 = inl_qrdmlsh_s16(env, src1 >> 16, src2 >> 16, src3 >> 16);
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return deposit32(e1, 16, 16, e2);
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}
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void HELPER(gvec_qrdmlsh_s16)(void *vd, void *vn, void *vm,
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void *ve, uint32_t desc)
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{
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uintptr_t opr_sz = simd_oprsz(desc);
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int16_t *d = vd;
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int16_t *n = vn;
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int16_t *m = vm;
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CPUARMState *env = ve;
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uintptr_t i;
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for (i = 0; i < opr_sz / 2; ++i) {
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d[i] = inl_qrdmlsh_s16(env, n[i], m[i], d[i]);
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}
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clear_tail(d, opr_sz, simd_maxsz(desc));
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}
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/* Signed saturating rounding doubling multiply-accumulate high half, 32-bit */
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uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1,
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int32_t src2, int32_t src3)
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{
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/* Simplify similarly to int_qrdmlah_s16 above. */
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int64_t ret = (int64_t)src1 * src2;
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ret = ((int64_t)src3 << 31) + ret + (1 << 30);
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ret >>= 31;
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if (ret != (int32_t)ret) {
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SET_QC();
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ret = (ret < 0 ? INT32_MIN : INT32_MAX);
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}
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return ret;
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}
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void HELPER(gvec_qrdmlah_s32)(void *vd, void *vn, void *vm,
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void *ve, uint32_t desc)
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{
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uintptr_t opr_sz = simd_oprsz(desc);
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int32_t *d = vd;
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int32_t *n = vn;
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int32_t *m = vm;
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CPUARMState *env = ve;
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uintptr_t i;
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for (i = 0; i < opr_sz / 4; ++i) {
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d[i] = helper_neon_qrdmlah_s32(env, n[i], m[i], d[i]);
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}
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clear_tail(d, opr_sz, simd_maxsz(desc));
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}
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/* Signed saturating rounding doubling multiply-subtract high half, 32-bit */
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uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1,
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int32_t src2, int32_t src3)
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{
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/* Simplify similarly to int_qrdmlsh_s16 above. */
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int64_t ret = (int64_t)src1 * src2;
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ret = ((int64_t)src3 << 31) - ret + (1 << 30);
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ret >>= 31;
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if (ret != (int32_t)ret) {
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SET_QC();
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ret = (ret < 0 ? INT32_MIN : INT32_MAX);
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}
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return ret;
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}
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void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void *vm,
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void *ve, uint32_t desc)
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{
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uintptr_t opr_sz = simd_oprsz(desc);
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int32_t *d = vd;
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int32_t *n = vn;
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int32_t *m = vm;
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CPUARMState *env = ve;
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uintptr_t i;
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for (i = 0; i < opr_sz / 4; ++i) {
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d[i] = helper_neon_qrdmlsh_s32(env, n[i], m[i], d[i]);
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}
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clear_tail(d, opr_sz, simd_maxsz(desc));
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}
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void HELPER(gvec_fcaddh)(void *vd, void *vn, void *vm,
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void *vfpst, uint32_t desc)
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{
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uintptr_t opr_sz = simd_oprsz(desc);
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float16 *d = vd;
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float16 *n = vn;
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float16 *m = vm;
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float_status *fpst = vfpst;
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uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1);
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uint32_t neg_imag = neg_real ^ 1;
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uintptr_t i;
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/* Shift boolean to the sign bit so we can xor to negate. */
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neg_real <<= 15;
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neg_imag <<= 15;
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for (i = 0; i < opr_sz / 2; i += 2) {
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float16 e0 = n[H2(i)];
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float16 e1 = m[H2(i + 1)] ^ neg_imag;
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float16 e2 = n[H2(i + 1)];
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float16 e3 = m[H2(i)] ^ neg_real;
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d[H2(i)] = float16_add(e0, e1, fpst);
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d[H2(i + 1)] = float16_add(e2, e3, fpst);
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}
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clear_tail(d, opr_sz, simd_maxsz(desc));
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}
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void HELPER(gvec_fcadds)(void *vd, void *vn, void *vm,
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void *vfpst, uint32_t desc)
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{
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uintptr_t opr_sz = simd_oprsz(desc);
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float32 *d = vd;
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float32 *n = vn;
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float32 *m = vm;
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float_status *fpst = vfpst;
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uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1);
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uint32_t neg_imag = neg_real ^ 1;
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uintptr_t i;
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/* Shift boolean to the sign bit so we can xor to negate. */
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neg_real <<= 31;
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neg_imag <<= 31;
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for (i = 0; i < opr_sz / 4; i += 2) {
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float32 e0 = n[H4(i)];
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float32 e1 = m[H4(i + 1)] ^ neg_imag;
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float32 e2 = n[H4(i + 1)];
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float32 e3 = m[H4(i)] ^ neg_real;
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d[H4(i)] = float32_add(e0, e1, fpst);
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d[H4(i + 1)] = float32_add(e2, e3, fpst);
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}
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clear_tail(d, opr_sz, simd_maxsz(desc));
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}
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void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm,
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void *vfpst, uint32_t desc)
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{
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uintptr_t opr_sz = simd_oprsz(desc);
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float64 *d = vd;
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float64 *n = vn;
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float64 *m = vm;
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float_status *fpst = vfpst;
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uint64_t neg_real = extract64(desc, SIMD_DATA_SHIFT, 1);
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uint64_t neg_imag = neg_real ^ 1;
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uintptr_t i;
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/* Shift boolean to the sign bit so we can xor to negate. */
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neg_real <<= 63;
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neg_imag <<= 63;
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for (i = 0; i < opr_sz / 8; i += 2) {
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float64 e0 = n[i];
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float64 e1 = m[i + 1] ^ neg_imag;
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float64 e2 = n[i + 1];
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float64 e3 = m[i] ^ neg_real;
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d[i] = float64_add(e0, e1, fpst);
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d[i + 1] = float64_add(e2, e3, fpst);
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}
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clear_tail(d, opr_sz, simd_maxsz(desc));
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}
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void HELPER(gvec_fcmlah)(void *vd, void *vn, void *vm,
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void *vfpst, uint32_t desc)
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{
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uintptr_t opr_sz = simd_oprsz(desc);
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float16 *d = vd;
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float16 *n = vn;
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float16 *m = vm;
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float_status *fpst = vfpst;
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intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
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uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
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uint32_t neg_real = flip ^ neg_imag;
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uintptr_t i;
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/* Shift boolean to the sign bit so we can xor to negate. */
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neg_real <<= 15;
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neg_imag <<= 15;
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for (i = 0; i < opr_sz / 2; i += 2) {
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float16 e2 = n[H2(i + flip)];
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float16 e1 = m[H2(i + flip)] ^ neg_real;
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float16 e4 = e2;
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float16 e3 = m[H2(i + 1 - flip)] ^ neg_imag;
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d[H2(i)] = float16_muladd(e2, e1, d[H2(i)], 0, fpst);
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d[H2(i + 1)] = float16_muladd(e4, e3, d[H2(i + 1)], 0, fpst);
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}
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clear_tail(d, opr_sz, simd_maxsz(desc));
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}
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void HELPER(gvec_fcmlah_idx)(void *vd, void *vn, void *vm,
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void *vfpst, uint32_t desc)
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{
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uintptr_t opr_sz = simd_oprsz(desc);
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float16 *d = vd;
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float16 *n = vn;
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float16 *m = vm;
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float_status *fpst = vfpst;
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intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
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uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
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uint32_t neg_real = flip ^ neg_imag;
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uintptr_t i;
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float16 e1 = m[H2(flip)];
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float16 e3 = m[H2(1 - flip)];
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/* Shift boolean to the sign bit so we can xor to negate. */
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neg_real <<= 15;
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neg_imag <<= 15;
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e1 ^= neg_real;
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e3 ^= neg_imag;
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for (i = 0; i < opr_sz / 2; i += 2) {
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float16 e2 = n[H2(i + flip)];
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float16 e4 = e2;
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d[H2(i)] = float16_muladd(e2, e1, d[H2(i)], 0, fpst);
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d[H2(i + 1)] = float16_muladd(e4, e3, d[H2(i + 1)], 0, fpst);
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}
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clear_tail(d, opr_sz, simd_maxsz(desc));
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}
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void HELPER(gvec_fcmlas)(void *vd, void *vn, void *vm,
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void *vfpst, uint32_t desc)
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{
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uintptr_t opr_sz = simd_oprsz(desc);
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float32 *d = vd;
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float32 *n = vn;
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float32 *m = vm;
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float_status *fpst = vfpst;
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intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
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uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
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uint32_t neg_real = flip ^ neg_imag;
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uintptr_t i;
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/* Shift boolean to the sign bit so we can xor to negate. */
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neg_real <<= 31;
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neg_imag <<= 31;
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for (i = 0; i < opr_sz / 4; i += 2) {
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float32 e2 = n[H4(i + flip)];
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float32 e1 = m[H4(i + flip)] ^ neg_real;
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float32 e4 = e2;
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float32 e3 = m[H4(i + 1 - flip)] ^ neg_imag;
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d[H4(i)] = float32_muladd(e2, e1, d[H4(i)], 0, fpst);
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d[H4(i + 1)] = float32_muladd(e4, e3, d[H4(i + 1)], 0, fpst);
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}
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clear_tail(d, opr_sz, simd_maxsz(desc));
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}
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void HELPER(gvec_fcmlas_idx)(void *vd, void *vn, void *vm,
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void *vfpst, uint32_t desc)
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{
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uintptr_t opr_sz = simd_oprsz(desc);
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float32 *d = vd;
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float32 *n = vn;
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float32 *m = vm;
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float_status *fpst = vfpst;
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intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
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uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
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uint32_t neg_real = flip ^ neg_imag;
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uintptr_t i;
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float32 e1 = m[H4(flip)];
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float32 e3 = m[H4(1 - flip)];
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/* Shift boolean to the sign bit so we can xor to negate. */
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neg_real <<= 31;
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neg_imag <<= 31;
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e1 ^= neg_real;
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e3 ^= neg_imag;
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for (i = 0; i < opr_sz / 4; i += 2) {
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float32 e2 = n[H4(i + flip)];
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float32 e4 = e2;
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d[H4(i)] = float32_muladd(e2, e1, d[H4(i)], 0, fpst);
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d[H4(i + 1)] = float32_muladd(e4, e3, d[H4(i + 1)], 0, fpst);
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}
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clear_tail(d, opr_sz, simd_maxsz(desc));
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}
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void HELPER(gvec_fcmlad)(void *vd, void *vn, void *vm,
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void *vfpst, uint32_t desc)
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{
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uintptr_t opr_sz = simd_oprsz(desc);
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float64 *d = vd;
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float64 *n = vn;
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float64 *m = vm;
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float_status *fpst = vfpst;
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intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
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uint64_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
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uint64_t neg_real = flip ^ neg_imag;
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uintptr_t i;
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/* Shift boolean to the sign bit so we can xor to negate. */
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neg_real <<= 63;
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neg_imag <<= 63;
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for (i = 0; i < opr_sz / 8; i += 2) {
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float64 e2 = n[i + flip];
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float64 e1 = m[i + flip] ^ neg_real;
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float64 e4 = e2;
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float64 e3 = m[i + 1 - flip] ^ neg_imag;
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d[i] = float64_muladd(e2, e1, d[i], 0, fpst);
|
|
d[i + 1] = float64_muladd(e4, e3, d[i + 1], 0, fpst);
|
|
}
|
|
clear_tail(d, opr_sz, simd_maxsz(desc));
|
|
}
|